IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 62

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

Table 42: Register List and Map (Continued)
Programming Information
IDT82V3280
Address
(Hex)
3A
3B
3C
3D
3E
35
36
37
38
39
3F
40
41
42
43
44
45
46
47
UPPER_THRESHOLD_1_CNFG
Upper Threshold for Leaky Bucket
Configuration 1
LOWER_THRESHOLD_1_CNFG
Lower Threshold for Leaky Bucket
Configuration 1
BUCKET_SIZE_1_CNFG - Bucket
Size for Leaky Bucket Configuration 1
DECAY_RATE_1_CNFG - Decay Rate
for Leaky Bucket Configuration 1
UPPER_THRESHOLD_2_CNFG
Upper Threshold for Leaky Bucket
Configuration 2
LOWER_THRESHOLD_2_CNFG
Lower Threshold for Leaky Bucket
Configuration 2
BUCKET_SIZE_2_CNFG - Bucket
Size for Leaky Bucket Configuration 2
DECAY_RATE_2_CNFG - Decay Rate
for Leaky Bucket Configuration 2
UPPER_THRESHOLD_3_CNFG
Upper Threshold for Leaky Bucket
Configuration 3
LOWER_THRESHOLD_3_CNFG
Lower Threshold for Leaky Bucket
Configuration 3
BUCKET_SIZE_3_CNFG - Bucket
Size for Leaky Bucket Configuration 3
DECAY_RATE_3_CNFG - Decay Rate
for Leaky Bucket Configuration 3
IN_FREQ_READ_CH_CNFG - Input
Clock Frequency Read Channel
Selection
IN_FREQ_READ_STS - Input Clock
Frequency Read Value
IN1_IN2_STS - Input Clock 1 & 2 Sta-
tus
IN3_IN4_STS - Input Clock 3 & 4 Sta-
tus
IN5_IN6_STS - Input Clock 5 & 6 Sta-
tus
IN7_IN8_STS - Input Clock 7 & 8 Sta-
tus
IN9_IN10_STS - Input Clock 9 & 10
Status
Register Name
-
-
-
-
-
-
Bit 7
-
-
-
-
-
-
-
-
-
IN2_FREQ
IN4_FREQ
IN6_FREQ
IN8_FREQ
IN10_FRE
Q_HARD_
_HARD_A
_HARD_A
_HARD_A
_HARD_A
ALARM
LARM
LARM
LARM
LARM
Bit 6
-
-
-
-
CTIVITY_A
CTIVITY_A
CTIVITY_A
CTIVITY_A
ACTIVITY_
IN2_NO_A
IN4_NO_A
IN6_NO_A
IN8_NO_A
IN10_NO_
ALARM
LARM
LARM
LARM
LARM
Bit 5
62
-
-
-
-
LOWER_THRESHOLD_1_DATA[7:0]
LOWER_THRESHOLD_2_DATA[7:0]
LOWER_THRESHOLD_3_DATA[7:0]
UPPER_THRESHOLD_1_DATA[7:0]
UPPER_THRESHOLD_2_DATA[7:0]
UPPER_THRESHOLD_3_DATA[7:0]
BUCKET_SIZE_1_DATA[7:0]
BUCKET_SIZE_2_DATA[7:0]
BUCKET_SIZE_3_DATA[7:0]
IN2_PH_L
OCK_ALA
IN4_PH_L
OCK_ALA
IN6_PH_L
OCK_ALA
IN8_PH_L
OCK_ALA
IN10_PH_
LOCK_AL
IN_FREQ_VALUE[7:0]
Bit 4
ARM
RM
RM
RM
RM
-
-
-
-
Bit 3
-
-
-
-
-
-
-
-
IN_FREQ_READ_CH[3:0]
IN1_FREQ
IN3_FREQ
IN5_FREQ
IN7_FREQ
IN9_FREQ
_HARD_A
_HARD_A
_HARD_A
_HARD_A
_HARD_A
LARM
LARM
LARM
LARM
LARM
Bit 2
-
-
-
CTIVITY_A
CTIVITY_A
CTIVITY_A
CTIVITY_A
CTIVITY_A
DECAY_RATE_1_DATA
DECAY_RATE_2_DATA
DECAY_RATE_3_DATA
IN1_NO_A
IN3_NO_A
IN5_NO_A
IN7_NO_A
IN9_NO_A
LARM
LARM
LARM
LARM
LARM
Bit 1
[1:0]
[1:0]
[1:0]
IN1_PH_L
OCK_ALA
IN3_PH_L
OCK_ALA
IN5_PH_L
OCK_ALA
IN7_PH_L
OCK_ALA
IN9_PH_L
OCK_ALA
December 9, 2008
Bit 0
RM
RM
RM
RM
RM
WAN PLL
Reference
P 104
P 104
P 105
P 105
P 105
P 106
P 106
P 106
P 107
P 107
P 107
P 108
P 108
P 109
P 109
P 110
P 111
P 112
P 113
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