IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 126

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

T0_BW_OVERSHOOT_CNFG - T0 DPLL Bandwidth Overshoot Configuration
Programming Information
IDT82V3280
Address: 59H
Type: Read / Write
Default Value: 1XXX1XXX
AUTO_BW_SEL
6 - 4
2 - 0
Bit
7
3
7
AUTO_BW_SEL
T0_LIMT
Name
-
-
6
-
This bit determines whether starting or acquisition bandwidth / damping factor is used for T0 DPLL.
0: The starting and acquisition bandwidths / damping factors are not used. Only the locked bandwidth / damping factor is used
regardless of the T0 DPLL locking stage.
1: The starting, acquisition or locked bandwidth / damping factor is used automatically depending on different T0 DPLL locking
stages. (default)
Reserved.
This bit determines whether the integral path value is frozen when the T0 DPLL hard limit is reached.
0: Not frozen.
1: Frozen. It will minimize the subsequent overshoot when T0 DPLL is pulling in. (default)
Reserved.
5
-
4
-
126
T0_LIMT
3
Description
2
-
1
-
December 9, 2008
0
-
WAN PLL