IDT82V3280PFG IDT, Integrated Device Technology Inc, IDT82V3280PFG Datasheet - Page 130

• Manufacturer Part Number: IDT82V3280PFG
• Description: IC PLL WAN SE STRATUM 2 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3280PFG

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3280PFG

T0_HOLDOVER_FREQ[15:8]_CNFG - T0 DPLL Holdover Frequency Configuration 2
T0_HOLDOVER_FREQ[23:16]_CNFG - T0 DPLL Holdover Frequency Configuration 3
Programming Information
Address: 5EH
Type: Read / Write
Default Value: 00000000
IDT82V3280
Address: 5FH
Type: Read / Write
Default Value: 00000000
T0_HOLDOVER
T0_HOLDOVER
_FREQ15
7 - 0
_FREQ23
7 - 0
Bit
Bit
7
7
T0_HOLDOVER_FREQ[23:16]
T0_HOLDOVER_FREQ[15:8] Refer to the description of the T0_HOLDOVER_FREQ[23:16] bits (b7~0, 5FH).
T0_HOLDOVER
T0_HOLDOVER
_FREQ14
_FREQ22
Name
Name
6
6
T0_HOLDOVER
T0_HOLDOVER
_FREQ13
_FREQ21
The T0_HOLDOVER_FREQ[23:0] bits represent a 2’s complement signed integer.
In T0 DPLL Holdover mode, the value written to these bits multiplied by 0.000011 is the frequency offset set manu-
ally; the value read from these bits multiplied by 0.000011 is the frequency offset automatically slow or fast aver-
aged or manually set, as determined by the READ_AVG bit (b4, 5CH) and the FAST_AVG bit (b5, 5CH).
5
5
T0_HOLDOVE
T0_HOLDOVE
R_FREQ12
R_FREQ20
4
4
130
T0_HOLDOVE
T0_HOLDOVE
R_FREQ11
R_FREQ19
3
3
Description
Description
T0_HOLDOVE
T0_HOLDOVE
R_FREQ10
R_FREQ18
2
2
T0_HOLDOVE
T0_HOLDOVE
R_FREQ17
R_FREQ9
1
1
December 9, 2008
T0_HOLDOVE
T0_HOLDOVE
R_FREQ16
R_FREQ8
0
0
WAN PLL