ISL12030IBZ Intersil, ISL12030IBZ Datasheet - Page 11

• Manufacturer Part Number: ISL12030IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12030IBZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ALARM Registers (1Dh to 28h)
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match.
There are two alarm operation modes: Single Event and
periodic Interrupt Mode.
Single Event Mode is enabled by setting either ALE0 or
ALE1 to 1, then setting bit 7 on any of the Alarm registers
(ESCA... EDWA) to “1”, and setting the IM bit to “0”. This
mode permits a one-time match between the Alarm registers
and the RTC registers. Once this match occurs, the ALM bit
is set to “1” and the IRQ output will be pulled LOW and will
remain LOW until the ALM bit is reset. This can be done
manually or by using the auto-reset feature. Since the IRQ
output is shared by both alarms, they both need to be reset
in order for the IRQ output to go HIGH.
Interrupt Mode is enabled by setting either ALE0 or ALE1 to
1, then setting bit 7 on any of the Alarm registers (ESCA...
EDWA) to “1”, and setting the IM bit to “1”. Setting the IM bit
to 1 puts both ALM0 and ALM1 into Interrupt mode. The IRQ
output will now be pulsed each time an alarm occurs (either
AL0 or AL1). This means that once the interrupt mode alarm
is set, it will continue to alarm until it is reset.
To clear a single event alarm, the corresponding ALM0 or
ALM1 bit in the SRDC register must be set to “0” with a write.
Note that if the ARST bit is set to “1” (address 0Ch, bit 7), the
ADDRESS
ADDRESS
1Ah
1Bh
1Ch
15h
16h
17h
18h
19h
Month Forward
Month Reverse
Hour Forward
Date Forward
Hour Reverse
Date Reverse
Day Forward
Day Reverse
FUNCTION
NAME
11
HrFdMIL
HrRvMIL
DSTE
7
0
0
7
0
0
0
DwFdE
DwRvE
6
0
0
6
0
0
0
0
TABLE 5. DST FORWARD REGISTERS
TABLE 6. DST REVERSE REGISTERS
HrFd21
DtRv21
HrRv21
DtFd21
WkFd12
WkRv12
5
0
5
0
ISL12030
MoRv20
MoFd20
DtRv20
HrRv20
HrFd20
DtFd20
WkRv11
WkFd11
ALM0 and ALM1 bits will automatically be cleared when the
status register is read.
The IRQ output will be set by an alarm match for either
ALM0 or ALM1.
Following are examples of both Single Event and periodic
Interrupt Mode alarms.
Example 1
• Alarm set with single interrupt (IM = ”0”)
• A single alarm will occur on January 1 at 11:30am.
• Set Alarm registers as follows:
After these registers are set, an alarm will be generated when
the RTC advances to exactly 11:30 a.m. on January 1 (after
seconds changes from 59 to 00) by setting the ALM0 bit in the
status register to “1” and also bringing the IRQ output LOW.
REGISTER
4
4
ALARM
MNA0
MOA0
DWA0
HRA0
SCA0
DTA0
MoRv13
MoFd13
HrRv13
DtRv13
DtFd13
HrFd13
WkRv10
WkFd10
7 6 5 4 3 2 1 0 HEX
0 0 0 0 0 0 0 0
1 0 1 1 0 0 0 0
1 0 0 1 0 0 0 1
1 0 0 0 0 0 0 1
1 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0
3
3
MoRv12
DwRv12
MoFd12
DwFd12
DtRv12
HrRv12
DtFd12
HrFd12
BIT
2
2
MoRv11
DwRv11
DwFd11
MoFd11
DtRv11
HrRv11
DtFd11
HrFd11
00h Seconds disabled
B0h Minutes set to 30,
91h Hours set to 11,
81h Date set to 1,
81h Month set to 1,
00h Day of week
1
1
enabled
enabled
enabled
enabled
disabled
DESCRIPTION
January 15, 2008
MoRv10
DwRv10
DwFd10
HrRv10
MoFd10
DtRv10
DtFd10
HrFd10
0
0
FN6617.1