ISL12030IBZ Intersil, ISL12030IBZ Datasheet - Page 14

• Manufacturer Part Number: ISL12030IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12030IBZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12030 responds with an ACK. At this time, the I
interface enters a standby state.
A multiple byte operation within a page is permitted. The
Address Byte must have the start address, and the data
bytes are sent in sequence after the address byte, with the
ISL12030 sending an ACK after each byte. The page write is
terminated with a STOP condition from the master. The
pages within the ISL12030 do not support wrapping around
for page read or write operations.
A7
D7
1
FIGURE 6. SLAVE ADDRESS, WORD ADDRESS AND DATA
FROM THE
SIGNALS
MASTER
SIGNALS FROM
SIGNAL AT
A6
D6
1
THE SLAVE
SDA
A5
D5
0
BYTES
S
A
R
T
T
A4
D4
1
1
IDENTIFICATION
1
BYTE WITH
A3
D3
0
1
R/W=0
1 1 1 1
14
1
A2
D2
0
FIGURE 7. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
1
A1
D1
A
C
K
R/W
A0
D0
ADDRESS
BYTE
SLAVE
ADDRESS BYTE
WORD ADDRESS
DATA BYTE
2
C
A
C
K
ISL12030
S
A
R
T
T
IDENTIFICATION
1
BYTE WITH
1
R/W = 1
0
1 1 1 1
Read Operation
A Read operation consists of a three byte instruction
followed by one or more Data Bytes (see Figure 7). The
master initiates the operation issuing the following
sequence: a START, the Identification byte with the RW bit
set to “0”, an Address Byte, a second START, and a second
Identification byte with the RW bit set to “1”. After each of the
three bytes, the ISL12030 responds with an ACK. Then the
ISL12030 transmits Data Bytes as long as the master
responds with an ACK during the SCL cycle following the
eighth bit of each byte. The master terminates the read
operation (issuing a STOP condition) following the last bit of
the last Data Byte (see Figure 7).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointers initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the last memory location in a section or page,
the master should issue a STOP. Bytes that are read at
addresses higher than the last address in a section may be
erroneous.
1
A
C
K
FIRST READ
DATA BYTE
A
C
K
A
C
K
LAST READ
DATA BYTE
January 15, 2008
FN6617.1
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