ISL12030IBZ Intersil, ISL12030IBZ Datasheet - Page 4

• Manufacturer Part Number: ISL12030IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12030IBZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
2
C Interface Specifications
SYMBOL
t
t
t
t
t
t
HD:DAT
SU:STO
HD:STO
SU:STA
HD:STA
SU:DAT
t
t
C
t
f
HIGH
LOW
SCL
t
BUF
t
t
Cb
AA
DH
t
PIN
t
IN
R
F
SDA and SCL Pin Capacitance
SCL Frequency
Pulse Width Suppression Time at
SDA and SCL Inputs
SCL Falling Edge to SDA Output
Data Valid
Time the Bus Must be Free Before
the Start of a New Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
START Condition Hold Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup Time
STOP Condition Hold Time
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive loading of SDA or SCL
PARAMETER
4
Specifications apply for: V
unless otherwise stated. (Continued)
T
V
V
Any pulse narrower than the
max spec is suppressed.
SCL falling edge crossing
30% of V
the 30% to 70% of V
window.
SDA crossing 70% of V
during a STOP condition, to
SDA crossing 70% of V
during the following START
condition.
Measured at the 30% of V
crossing.
Measured at the 70% of V
crossing.
SCL rising edge to SDA
falling edge. Both crossing
70% of V
From SDA falling edge
crossing 30% of V
falling edge crossing 70% of
V
From SDA exiting the 30% to
70% of V
rising edge crossing 30% of
V
From SCL falling edge
crossing 30% of V
entering the 30% to 70% of
V
From SCL rising edge
crossing 70% of V
rising edge crossing 30% of
V
From SDA rising edge to
SCL falling edge. Both
crossing 70% of V
From SCL falling edge
crossing 30% of V
SDA enters the 30% to 70%
of V
From 30% to 70% of V
From 70% to 30% of V
Total on-chip and off-chip
A
DD
OUT
DD
DD.
DD
DD
= +25°C, f = 1MHz,
DD
TEST CONDITIONS
.
.
= 5V, V
window.
= 0V
window.
DD
ISL12030
DD
DD
DD
= 2.7 to 5.5V, T
, until SDA exits
.
IN
window, to SCL
= 0V,
DD
DD
DD
DD
DD
DD
, to SDA
.
, until
to SDA
to SCL
DD.
DD.
DD
DD
DD
DD
A
= -40°C to +85°C,
20 + 0.1 x Cb
20 + 0.1 x Cb
(Note 8)
1300
1300
MIN
600
600
600
100
600
600
10
0
0
(Note 3)
TYP
10
(Note 8)
MAX
400
900
900
300
300
400
50
UNITS
kHz
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
January 15, 2008
NOTES
FN6617.1
7
7
7