ISL12030IBZ Intersil, ISL12030IBZ Datasheet - Page 13

• Manufacturer Part Number: ISL12030IBZ
• Description: IC RTC/CALENDAR EEPROM 8-SOIC
• Manufacturer: Intersil
• Type: Clock/Calendar/NVSRAMr

Specifications of ISL12030IBZ

• Memory Size: 1K (128 x 8)
• Time Format: HH:MM:SS:hh (12/24 hr)
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifier. These bits
are “1101111b” for the RTC registers and “1010111b” for the
User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, then a
read operation is selected. A “0” selects a write operation (see
Figure 6).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12030 compares the device identifier and device select
bits with “1101111b” or “1010111b”. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
SDA OUTPUT FROM
SDA OUTPUT FROM
TRANSMITTER
SCL FROM
RECEIVER
SDA
SCL
MASTER
SIGNALS FROM
SIGNAL AT SDA
SIGNALS FROM
THE MASTER
THE ISL12030
13
FIGURE 5. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
START
FIGURE 3. VALID DATA CHANGES, START AND STOP CONDITIONS
START
FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER
HIGH IMPEDANCE
S
T
A
R
T
1
IDENTIFICATION
1
1
0
BYTE
1
STABLE
1 1 1
DATA
ISL12030
0
WRITE
A
C
K
CHANGE
DATA
0 0 0 0
ADDRESS
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Byte as shown in
Figure 6.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
BYTE
STABLE
DATA
A
C
K
8
DATA
BYTE
HIGH IMPEDANCE
STOP
ACK
9
A
C
K
S
T
O
P
January 15, 2008
FN6617.1