MAX132CWG+ Maxim Integrated Products, MAX132CWG+ Datasheet - Page 10

• Manufacturer Part Number: MAX132CWG+
• Description: IC ADC 18BIT W/SRL INTRFC 24SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX132CWG+

• Number Of Bits: 18
• Sampling Rate (per Second): 100
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Architecture: Dual Slope
• Conversion Rate: 0.1 KSPs
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 647 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±18-Bit ADC with Serial Interface
Serial data at DIN is sent in 8-bit packets and is shifted
into the internal 8-bit shift register with each rising edge
of SCLK. The data is then latched into either command
input register 0 or command input register 1, as deter-
mined by the LSB of the data sent, and is latched on
the rising edge of CHIP SELECT (CS) Data is clocked
out of the selected output register on each falling edge
of SCLK. D7(MSB) must be the first data bit to be shift-
ed in and is the first bit to be shifted out.
Output data is shifted out at the same time command
data is shifted in. Command data must be clocked in
on the previous 8-bit read-write cycle to receive con-
version data in the present cycle.
Since there is no internal power-on reset, initialize the
MAX132 immediately after power-up to insure correct
operation.
Table 2 defines each bit of five registers: the two com-
mand input registers, output register 0, output register
1, and the status output register.
Data bits D1 and D2 of command register 0 (RS1 and
RS0) determine the data to be read on the data bus.
These bits select which register outputs data to the bus.
Table 3 defines the bit values that determine which reg-
ister is read on the next cycle (Figure 9).
Table 2. Register Map of Input and Output Data
*Note: Refer to Table 3.
10
___________________Digital Interface
Command Input
Register 0
Command Input
Register 1
Output Register 0
RS1 = 0, RS0 = 0
Output Register 1
RS1 = 0, RS0 = 1
Output Status
Register
RS1 = 1, RS0 = 0
______________________________________________________________________________________
REGISTER
Command Input Register 0
“1”
“0”
“1”
“0”
No Collision Converting
Returns to
0 at EOC
Collision
Convert
Output
Set P3
MSB
Start
B10
B18
D7
Register-Set Bits
Output
Set P2
50Hz
60Hz
EOC
B17
D6
B9
Integrating
Integrating
Awake
Output
Set P1
Sleep
Input
B16
Not
D5
B8
The read-zero bit allows the ADC to calibrate on com-
mand for zero offset. The read-zero bit, when set to 1,
internally shorts the inputs; when a start-conversion
command is given, the zero error is converted. Subtract
the results from the standard external measurement
conversion when the read-zero conversion ends. If the
read-zero bit is set to 0, the converter measures the
voltage between IN Hl and IN LO once a start bit is
given. Take a new zero reading periodically and when-
ever the ambient temperature, the reference voltage, or
the common-mode input voltage are changed.
Figure 9. Instruction and Data Sequencing
Table 3. Register Set-Bit Definitions
Read Zero
OUTPUT DATA
INSTRUCTION
RS1
Read V
Output
0
0
1
1
Set P0
Awake
Sleep
REGISTER
B15
D4
B7
(DATA IN)
DATA BIT
RS0
IN
0
1
0
1
Don’t Care
Don’t Care
Don’t Care
READ STATUS
+Polarity
CYCLE 1
-Polarity
Selects Register 0; output for data bits B3–B10
Selects Register 1; output for data bits B11–B18
Selects Register 2; output status for data bits
B0–B2, polarity, sleep, integrating, EOC, and
collision bit
Invalid data
START,
B14
D3
B6
(EOC, POLARITY, B2–B0)
READ HIGHER
OUTPUT STATUS
Don’t Care
CYCLE 2
REGISTER
BITS
RS0*
B13
D2
B5
B2
DEFINITIONS
READ LOWER
Don’t Care
CYCLE 3
BITS
REGISTER 1
( B11–B18)
RS1*
B12
D1
B4
B1
Read-Zero Bit
READ STATUS
CYCLE 4
START,
REGISTER 0
( B3–B10)
LSB
B11
D0
B3
B0
0
1