MAX132CWG+ Maxim Integrated Products, MAX132CWG+ Datasheet - Page 12

• Manufacturer Part Number: MAX132CWG+
• Description: IC ADC 18BIT W/SRL INTRFC 24SOIC
• Manufacturer: Maxim Integrated Products

Specifications of MAX132CWG+

• Number Of Bits: 18
• Sampling Rate (per Second): 100
• Data Interface: MICROWIRE™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 24-SOIC (0.300", 7.50mm Width)
• Architecture: Dual Slope
• Conversion Rate: 0.1 KSPs
• Input Type: Voltage
• Interface Type: 4-Wire (SPI, QSPI, MICROWIRE, TMS320)
• Supply Voltage (max): 5 V
• Maximum Power Dissipation: 647 mW
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

±18-Bit ADC with Serial Interface
Table 4. Overrange Values for
Resolution Used
Table 5. Output Values for 16-Bit
Resolution (Offset Corrected)
* Soft Overrange Operation
Note: The MAX132 exhibits additional errors when operating
in the soft overrange area. Operation in this region is not
included in the specifications. The soft overrange values listed
in Table 5 do not include error correction.
12
B18–B3
B18–B2
B18–B1
B18–B0
+640mV
+576mV
+545mV
+512mV
+448mV
+384mV
+320mV
+256mV
+192mV
+128mV
-128mV
-192mV
-256mV
-320mV
-384mV
-448mV
-512mV
-545mV
-576mV
-640mV
+64mV
Used
+15µV
-64mV
-15µV
Bits
Input
______________________________________________________________________________________
0
Resolution
Hexadecimal
Bits
Reading
±15
±16
±17
±18
+A000
+9000
+8840
+8000
+7000
+6000
+5000
+4000
+3000
+2000
+1000
+0001
+0000
-E000
-D000
-C000
-B000
-A000
-77C0
-FFFF
-F000
-9000
-8000
-7000
-6000
Soft Overrange
Start Value
Decimal
+40960*
+36864*
+34880*
139,520
279,040
Counts
+32768
+28672
+24576
+20480
+16384
+12288
-34880*
-36864*
-40960*
34,880
69,760
-12288
-16384
-20480
-24576
-28672
-32768
+8192
+4096
-4096
-8192
+1
-1
0
Positive Reference
Voltage
Positive Full Scale
Negative Full Scale
Negative Reference
Voltage
Hard Overrange
Maximum Value
Comment
175,220
350,440
43,805
87,610
Command input register 1 always has data bit D0 = 1.
Data bits D4 to D7 of command register 1 control the
states of the user-programmable output pins P0 to P3,
respectively (Table 2). These four outputs can be used
to control an external multiplexer, programmable gain
amplifier, or other devices.
Output data is the sum of system offset (read zero) plus
the results of the external input voltage measurement.
Register 0 contains the low-byte (bits B3–B10) conver-
sion data. New data is available after EOC goes high.
Access register 0 by setting RS0 and RS1 to 0.
Register 1 contains the high-byte (bits B11–B18) data.
Data is in a twos-complement format‚ where the polarity
bit is a 1 for negative polarity data. Access register 1
by setting control bits RS0 = 1 and RS1 = 0 when writ-
ing to the command input register.
The B0, B1, and B2 bits are located in the status regis-
ter. At the end of each conversion these bits are updat-
ed and read back from the status register. For full
18-bit resolution, use bits B0–B2. Average multiple
results to increase accuracy. The polarity bit informa-
tion is necessary to determine if the reading is not in
overrange (Tables 4 and 5).
The integrate (INT) bit is set to 1 at the beginning of the
integration phase and becomes 0 at the end. Poll INT
to determine the earliest time the input can be changed
without affecting the conversion.
The end-of-conversion (EOC) bit signals conversion sta-
tus. If EOC is 1, the conversion is complete and the ADC
waits in zero-integrate mode at time = 0000 for the next
start instruction. A conversion cycle has 2048 counts.
EOC becomes 1 at count 0000 and 0 at count 0001.
The collision bit warns the microprocessor (µP) that the
register’s data was changed during the read cycle. A
collision occurs if the internal result latches on the falling
edge of CS, causing the collision bit to be set to 1 on the
rising edge of the next CS. This occurs because these
two pulses are asynchronous. Once the status register is
User-Programmable Output Bits P0 to P3
Command Input Register 1
End-of-Conversion Bit
Output Registers
Status Register
Integrate Bit
Collision Bit
Bits B0–B2
Register 0
Register 1