AD5175BRMZ-10 Analog Devices Inc, AD5175BRMZ-10 Datasheet - Page 18

• Manufacturer Part Number: AD5175BRMZ-10
• Description: IC DGTL POT 1024POS 10K 10MSOP
• Manufacturer: Analog Devices Inc

Specifications of AD5175BRMZ-10

• Taps: 1024
• Resistance (ohms): 10K
• Number Of Circuits: 1
• Temperature Coefficient: 35 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.7 V ~ 5.5 V, ±2.5 V ~ 2.75 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resistance In Ohms: 10K
• End To End Resistance: 10kohm
• Resistance Tolerance: -15% To +15%
• No. Of Steps: 1024
• Supply Voltage Range: 2.7V To 5.5V, ± 2.7V
• Control Interface: I2C, Serial
• No. Of Pots: Single
• Memory: RoHS Compliant
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5175
50-TP MEMORY WRITE-ACKNOWLEDGE POLLING
After each write operation to the 50-TP registers, an internal
write cycle begins. The I
To determine if the internal write cycle is complete and the
I
interface polling can be conducted by sending a start condition
followed by the slave address and the write bit. If the I
face responds with an acknowledge (ACK), the write cycle is
complete and the interface is ready to proceed with further
operations. Otherwise, I
until it completes.
RESET
The AD5175 can be reset through software by executing
Command 4 (see Table 7) or through hardware on the low
pulse of the RESET pin. The reset command loads the RDAC
register with the contents of the most recently programmed
50-TP memory location. The RDAC register loads with
midscale if no 50-TP memory location has been previously
programmed. Tie RESET to V
SHUTDOWN MODE
The AD5175 can be shut down by executing the software
shutdown command, Command 9 (see Table 7), and setting
the LSB to 1. This feature places the RDAC in a zero-power-
consumption state where Terminal A is disconnected from the
wiper terminal. It is possible to execute any command from
Table 7 while the AD5175 is in shutdown mode. The part can
be taken out of shutdown mode by executing Command 9 and
setting the LSB to 0, or by issuing a software or hardware reset.
2
C interface is enabled, interface polling can be executed. I
2
2
C interface of the device is disabled.
C interface polling can be repeated
DD
if the RESET pin is not used.
2
C inter-
2
C
Rev. A | Page 18 of 20
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5175 employs a
three-stage segmentation approach, as shown in Figure 28.
The AD5175 wiper switch is designed with the transmission
gate CMOS topology.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance between Terminal W and Terminal A,
R
the wiper terminal. The 10-bit data in the RDAC latch is decoded
to select one of the 1024 possible wiper settings. As a result, the
general equation for determining the digitally programmed
output resistance between the W terminal and A terminal is
where:
D is the decimal equivalent of the binary code loaded in the
10-bit RDAC register.
R
In the zero-scale condition, a finite total wiper resistance of
120 Ω is present. Regardless of which setting the part is oper-
ating in, take care to limit the current between the A terminal
to W terminal, and W terminal to B terminal, to the maximum
continuous current of ±6 mA, or the pulse current specified in
Table 3. Otherwise, degradation or possible destruction of the
internal switch contact can occur.
WA
WA
, is available in 10 kΩ and has 1024-tap points accessed by
is the end-to-end resistance.
R
WA
ADDRESS
DECODER
10-BIT
(
D
)
=
1024
D
Figure 28. Simplified RDAC Circuit
A
×
R
WA
R
R
L
L
R
R
R
R
M
M
W
W
S
W
W
(1)