X9221AWS Intersil, X9221AWS Datasheet - Page 2

• Manufacturer Part Number: X9221AWS
• Description: IC XDCP DUAL 10K 2-WIRE 20-SOIC
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of X9221AWS

• Taps: 64
• Resistance (ohms): 10K
• Number Of Circuits: 2
• Temperature Coefficient: 30 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-SOIC (7.5mm Width)
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9221A.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
Address
The Address inputs are used to set the least signifi-
cant 4 bits of the 8-bit slave address. A match in the
slave address serial data stream must be made with
the Address input in order to initiate communication
with the X9221A
Ordering Information
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
X9221AYS
X9221AYSZ (Note)
X9221AYSI*
X9221AYSIZ* (Note)
X9221AWS*
X9221AWSZ* (Note)
X9221AWSI*
X9221AWSIZ* (Note)
X9221AUP
X9221AUPZ (Note)
X9221AUPI
X9221AUPIZ (Note)
X9221AUSI*
X9221AUSIZ* (Note)
PART NUMBER
X9221AYS
X9221AYS Z
X9221AYSI
X9221AYSI Z
X9221AWS
X9221AWS Z
X9221AWSI
X9221AWSI Z
X9221AUP
X9221AUPZ
X9221AUPI
X9221AUPIZ
X9221AUSI
X9221AUSI Z
PART MARKING
2
V
CC
5 ±10%
(V)
LIMITS
X9221A
R
TOTAL
10
50
2
(k)
Potentiometer Pins
V
The V
minal connections on either end of a mechanical
potentiometer.
V
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
PIN CONFIGURATION
H
W
RANGE (°C)
/R
/R
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
0 to +70
H
TEMP
W
H
(V
/R
(V
H0
H
W0
V
V
/R
V
V
W0
V
W1
V
and V
H1
H0
L0
L1
H0
/R
/R
/R
SDA
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
20 Ld PDIP
20 Ld PDIP (Pb-Free)
20 Ld PDIP
20 Ld PDIP (Pb-Free)
20 Ld SOIC (300MIL)
20 Ld SOIC (300MIL) (Pb-Free)
/R
/R
V
/R
/R
W0
SS
-V
W0
W1
A0
A2
H1
L0
L0
L1
L
H1
-V
/R
/R
W1
L
1
2
3
4
5
6
7
8
9
10
H1
inputs are equivalent to the ter-
PACKAGE
/R
DIP/SOIC
), V
X9221A
W1
L
)
/R
L
20
19
18
17
16
15
14
13
12
11
(V
L0
/R
V
RES
RES
RES
A1
A3
SCL
RES
RES
RES
L0
CC
-V
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0027
MDP0031
MDP0031
MDP0031
MDP0031
MDP0027
MDP0027
August 30, 2006
DWG. #
L1
PKG.
/R
FN8163.2
L1
)