ISL22343WFR20Z-TK Intersil, ISL22343WFR20Z-TK Datasheet - Page 13

• Manufacturer Part Number: ISL22343WFR20Z-TK
• Description: IC POT DGTL 256TP LN LP 20-QFN
• Manufacturer: Intersil
• Series: XDCP™r

Specifications of ISL22343WFR20Z-TK

• Taps: 256
• Resistance (ohms): 10K
• Number Of Circuits: 4
• Temperature Coefficient: 85 ppm/°C Typical
• Memory Type: Non-Volatile
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 2.25 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 20-TQFN Exposed Pad
• Resistance In Ohms: 10K
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

same time, the resistance between RWi and RLi increases
monotonically, while the resistance between RHi and RWi
decreases monotonically.
While the ISL22343 is being powered up, the WRi is reset to
80h (128 decimal), which locates RWi roughly at the center
between RLi and RHi. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, the WRi will be reloaded with the value stored in
corresponding non-volatile Initial Value Register (IVRi).
The WRi and IVRi can be read or written to directly using the
I
Memory Description
The ISL22343 contains four non-volatile 8-bit Initial Value
Register (IVRi), eleven General Purpose non-volatile 8-bit
registers and five volatile 8-bit registers: four Wiper Registers
(WRi) and Access Control Register (ACR). Memory map of
ISL22343 is in Table 1. The non-volatile registers (IVRi) at
address 0, 1, 2 and 3 contain initial wiper position and volatile
registers (WRi) contain current wiper position.
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
2
ADDRESS
C serial interface as described in the following sections.
(hex)
10
E
D
C
B
A
F
9
8
7
6
5
4
3
2
1
0
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
NON-VOLATILE
TABLE 1. MEMORY MAP
IVR3
IVR2
IVR1
IVR0
N/A
13
Reserved
VOLATILE
WR3
WR2
WR1
WR0
ACR
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ISL22343
The VOL bit (ACR[7]) determines whether the access to
wiper registers WRi or initial value registers IVRi.
If VOL bit is 0, the non-volatile IVRi registers are accessible.
If VOL bit is 1, only the volatile WRi are accessible.
Note: value is written to IVRi register also is written to the
corresponding WRi. The default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown mode.
When this bit is 0, DCPs are in Shutdown mode. Default value
of the SHDN bit is 1.
The WIP bit (ACR[5]) is a read-only bit. It indicates that non-
volatile write operation is in progress. It is impossible to write
to the WRi or ACR while WIP bit is 1.
I
The ISL22343 supports an I
protocol. The protocol defines any device that sends data onto
the bus as a transmitter and the receiving device as the
receiver. The device controlling the transfer is a master and
the device being controlled is the slave. The master always
initiates data transfers and provides the clock for both transmit
and receive operations. Therefore, the ISL22343 operates as
a slave device in all applications.
All communication over the I
sending the MSB of each byte of data first.
Protocol Conventions
Data states on the SDA line must change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating START and STOP conditions
(see Figure 16). On power-up of the ISL22343, the SDA pin
is in the input mode.
All I
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The ISL22343 continuously monitors the SDA
and SCL lines for the START condition and does not
respond to any command until this condition is met (See
Figure 16). A START condition is ignored during the power-
up of the device.
All I
condition, which is a LOW to HIGH transition of SDA while
2
NAME
BIT #
C Serial Interface
2
2
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
C interface operations must begin with a START
C interface operations must be terminated by a STOP
TABLE 2. ACCESS CONTROL REGISTER (ACR)
VOL
7
SHDN
6
WIP
5
2
C bidirectional bus oriented
2
4
0
C interface is conducted by
RHi
RWi
RLi
3
0
2
0
March 13, 2008
1
0
FN6423.1
0
0