ISL22343WFR20Z-TK Intersil, ISL22343WFR20Z-TK Datasheet - Page 7

IC POT DGTL 256TP LN LP 20-QFN

ISL22343WFR20Z-TK

Manufacturer Part Number
ISL22343WFR20Z-TK
Description
IC POT DGTL 256TP LN LP 20-QFN
Manufacturer
Intersil
Series
XDCP™r
Datasheet

Specifications of ISL22343WFR20Z-TK

Taps
256
Resistance (ohms)
10K
Number Of Circuits
4
Temperature Coefficient
85 ppm/°C Typical
Memory Type
Non-Volatile
Interface
I²C, 2-Wire Serial
Voltage - Supply
2.25 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TQFN Exposed Pad
Resistance In Ohms
10K
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISL22343WFR20Z-TK
Manufacturer:
SIEMENS
Quantity:
100
Operating Specifications
SERIAL INTERFACE SPECS
Hysteresis
SYMBOL
(Note 19)
(Note 19)
(Note 19)
(Note 19)
(Note 19)
(Note 19)
(Note 19)
(Note 19)
t
t
t
t
t
t
SU:STO
HD:STO
SU:STA
HD:STA
SU:DAT
HD:DAT
t
t
Cpin
f
t
V
HIGH
LOW
V
BUF
t
V
SCL
t
t
DH
AA
t
t
sp
OL
R
IH
F
IL
A1, A0, A2, SDA, and SCL
Input Buffer LOW Voltage
A1, A0, A2, SDA, and SCL
Input Buffer HIGH Voltage
SDA and SCL Input Buffer
Hysteresis
SDA Output Buffer LOW
Voltage, Sinking 4mA
A1, A0, A2, SDA, and SCL
Pin Capacitance
SCL Frequency
Pulse Width Suppression
Time at SDA and SCL
Inputs
SCL Falling Edge to SDA
Output Data Valid
Time the Bus Must be Free
Before the Start of a New
Transmission
Clock LOW Time
Clock HIGH Time
START Condition Setup
Time
START Condition Hold
Time
Input Data Setup Time
Input Data Hold Time
STOP Condition Setup
Time
STOP Condition Hold
Time for Read, or Volatile
Only Write
Output Data Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
PARAMETER
7
Over the recommended operating conditions unless otherwise specified. (Continued)
From 30% to 70% of V
Any pulse narrower than the max spec is suppressed
SCL falling edge crossing 30% of V
the 30% to 70% of V
SDA crossing 70% of V
SDA crossing 70% of V
condition
Measured at the 30% of V
Measured at the 70% of V
SCL rising edge to SDA falling edge; both crossing 70%
of V
From SDA falling edge crossing 30% of V
falling edge crossing 70% of V
From SDA exiting the 30% to 70% of V
SCL rising edge crossing 30% of V
From SCL rising edge crossing 70% of V
entering the 30% to 70% of V
From SCL rising edge crossing 70% of V
rising edge crossing 30% of V
From SDA rising edge to SCL falling edge; both
crossing 70% of V
From SCL falling edge crossing 30% of V
enters the 30% to 70% of V
From 70% to 30% of V
CC
TEST CONDITIONS
CC
CC
ISL22343
CC
CC
CC
CC
window
CC
CC
during a STOP condition, to
during the following START
CC
CC
crossing
crossing
CC
CC
window
window
CC
CC
, until SDA exits
CC
CC
CC
CC
CC
window, to
, until SDA
, to SDA
to SDA
to SCL
(Note 21)
0.05*V
0.7*V
0.1*Cb
0.1*Cb
1300
1300
1300
20 +
20 +
MIN
600
600
600
100
600
0
0
0
CC
CC
(Note 5)
TYP
(Note 21)
0.3*V
MAX
400
900
250
250
0.4
10
50
CC
March 13, 2008
UNIT
kHz
FN6423.1
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
V
V

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