MT47H128M8HQ-187E:E Micron Technology Inc, MT47H128M8HQ-187E:E Datasheet - Page 30

• Manufacturer Part Number: MT47H128M8HQ-187E:E
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-187E:E

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 350ps
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 210mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 10: DDR2 Idd Specifications and Conditions (Die Revisions E and G) (Continued)
Notes: 1–7 apply to the entire table
PDF: 09005aef821ae8bf
Rev. O 9/08 EN
Parameter/Condition
Operating bank interleave read
current: All bank interleaving
reads, Iout = 0mA; BL = 4, CL = CL
(Idd), AL =
(Idd);
t
t
is HIGH between valid commands;
Address bus inputs are stable dur-
ing deselects; Data bus inputs are
switching; See Idd7 Conditions
(page 27) for details
RC =
RCD =
t
t
RC (Idd),
CK =
t
RCD (Idd); CKE is HIGH, CS#
t
RCD (Idd) - 1 ×
t
CK (Idd),
t
RRD =
Notes:
t
RRD (Idd),
t
CK
1. Idd specifications are tested after the device is properly initialized. 0°C ≤ T
2. Vdd = +1.8V ±0.1V, VddQ = +1.8V ±0.1V, VddL = +1.8V ±0.1V, Vref = VddQ/2.
3. Idd parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
5. Definitions for Idd conditions:
6. Idd1, Idd4R, and Idd7 require A12 in EMR to be enabled during testing.
7. The following Idd values must be derated (Idd limits increase) on IT-option and AT-op-
UDQS#. Idd values must be met with all combinations of EMR bits 10 and 11.
tion devices when operated outside of the range 0°C ≤ T
LOW
HIGH
Stable
Floating
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
Switching Inputs changing between HIGH and LOW every other data transfer (once
When
T
When
T
C
C
≤ 0°C
≥ 85°C
Symbol
Idd7
Idd2P and Idd3P (slow) must be derated by 4 percent; Idd4R and Idd5W
must be derated by 2 percent; and Idd6 and Idd7 must be derated by 7 percent
Idd0, Idd1, Idd2N, Idd2Q, Idd3N, Idd3P (fast), Idd4R, Idd4W, and Idd5W
must be derated by 2 percent; Idd2P must be derated by 20 percent; Idd3P
slow must be derated by 30 percent; and Idd6 must be derated by 80 per-
cent (Idd6 will increase by this amount if T
option is still enabled)
Vin ≤ Vil(AC) MAX
Vin ≥ Vih(AC) MIN
Inputs stable at a HIGH or LOW level
Inputs at Vref = VddQ/2
two clocks) for address and control signals
per clock) for DQ signals, not including masks or strobes
Configuration
x4, x8
x16
30
Electrical Specifications – Idd Parameters
-187E
425
520
Micron Technology, Inc. reserves the right to change products or specifications without notice.
-25E/
335
440
-25
1Gb: x4, x8, x16 DDR2 SDRAM
-3E/
280
350
-3
C
< 85°C and the 2X refresh
C
≤ 85°C:
© 2004 Micron Technology, Inc. All rights reserved.
-37E
270
330
260
300
-5E
C
≤ +85°C.
Units
mA