MT47H128M8HQ-187E:E Micron Technology Inc, MT47H128M8HQ-187E:E Datasheet - Page 71

• Manufacturer Part Number: MT47H128M8HQ-187E:E
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-187E:E

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 350ps
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 210mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 37: Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6 apply to the entire table
PDF: 09005aef821ae8bf
Rev. O 9/08 EN
Current
State
Any
Idle
Row active
Read (auto
precharge
disabled)
Write
(auto pre-
charge disa-
bled)
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
Notes:
RAS#
X
H
H
H
H
H
H
H
L
L
L
L
L
L
5. An n is the most significant address bit for a given density and configuration. Some larg-
6. Bank addresses (BA) determine which bank is to be operated upon. BA during a LOAD
7. SELF REFRESH exit is asynchronous.
8. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 47
9. The power-down mode does not perform any REFRESH operations. The duration of power-
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after
2. This table is bank-specific, except where noted (the current state is for a specific bank
3. Current state definitions:
CAS#
er address bits may be “Don’t Care” during column addressing, depending on density
and configuration.
MODE command selects which mode register is programmed.
(page 98) and Figure 59 (page 109) for other restrictions and details.
down is limited by the refresh requirements outlined in the AC parametric section.
met (if the previous state was self refresh).
and the commands shown are those allowed to be issued to that bank when in that
state). Exceptions are covered in the notes below.
Idle:
Row
active:
Read:
Write: A WRITE burst has been initiated with auto precharge disabled and has not
X
H
H
H
H
H
L
L
L
L
L
L
L
L
The bank has been precharged,
plete.
A row in the bank has been activated, and
accesses and no register accesses are in progress.
A READ burst has been initiated, with auto precharge disabled and has not
yet terminated.
yet terminated.
WE#
X
H
H
H
H
H
H
L
L
L
L
L
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
ACTIVATE (select and activate row)
REFRESH
LOAD MODE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (start PRECHARGE)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (start PRECHARGE)
71
Command/Action
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
RP has been met, and any READ burst is com-
1Gb: x4, x8, x16 DDR2 SDRAM
t
RCD has been met. No data bursts/
© 2004 Micron Technology, Inc. All rights reserved.
t
XSNR has been
Commands
Notes
8, 10
7
7
8
8
9
8
9
8
8
9