MT47H128M8HQ-187E:E Micron Technology Inc, MT47H128M8HQ-187E:E Datasheet - Page 7

• Manufacturer Part Number: MT47H128M8HQ-187E:E
• Manufacturer: Micron Technology Inc
• Type: DDR2 SDRAMr

Specifications of MT47H128M8HQ-187E:E

• Organization: 128Mx8
• Density: 1Gb
• Address Bus: 17b
• Access Time (max): 350ps
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 210mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

List of Figures
Figure 1: 1Gb DDR2 Part Numbers ................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 9
Figure 3: 256 Meg x 4 Functional Block Diagram ............................................................................................. 12
Figure 4: 128 Meg x 8 Functional Block Diagram ............................................................................................. 13
Figure 5: 64 Meg x 16 Functional Block Diagram ............................................................................................. 14
Figure 6: 60-Ball FBGA – x4, x8 Ball Assignments (Top View) ........................................................................... 15
Figure 7: 84-Ball FBGA – x16 Ball Assignments (Top View) .............................................................................. 16
Figure 8: 84-Ball FBGA Package (8mm x 12.5mm) – x16 ................................................................................... 20
Figure 9: 60-Ball FBGA Package (8mm x 11.5mm) – x4, x8 ............................................................................... 21
Figure 10: Example Temperature Test Point Location ..................................................................................... 24
Figure 11: Single-Ended Input Signal Levels ................................................................................................... 44
Figure 12: Differential Input Signal Levels ...................................................................................................... 45
Figure 13: Differential Output Signal Levels .................................................................................................... 47
Figure 14: Output Slew Rate Load .................................................................................................................. 48
Figure 15: Full Strength Pull-Down Characteristics ......................................................................................... 49
Figure 16: Full Strength Pull-Up Characteristics ............................................................................................. 50
Figure 17: Reduced Strength Pull-Down Characteristics ................................................................................. 51
Figure 18: Reduced Strength Pull-Up Characteristics ...................................................................................... 52
Figure 19: Input Clamp Characteristics .......................................................................................................... 53
Figure 20: Overshoot ..................................................................................................................................... 54
Figure 21: Undershoot .................................................................................................................................. 54
Figure 22: Nominal Slew Rate for
Figure 23: Tangent Line for
Figure 24: Nominal Slew Rate for
Figure 25: Tangent Line for
Figure 26: Nominal Slew Rate for
Figure 27: Tangent Line for
Figure 28: Nominal Slew Rate for
Figure 29: Tangent Line for
Figure 30: AC Input Test Signal Waveform Command/Address Balls ............................................................... 68
Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) ........................................... 68
Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) .................................................. 69
Figure 33: AC Input Test Signal Waveform (Differential) ................................................................................. 69
Figure 34: MR Definition ............................................................................................................................... 77
Figure 35: CL ................................................................................................................................................ 81
Figure 36: EMR Definition ............................................................................................................................. 82
Figure 37: READ Latency ............................................................................................................................... 85
Figure 38: WRITE Latency ............................................................................................................................. 85
Figure 39: EMR2 Definition ........................................................................................................................... 86
Figure 40: EMR3 Definition ........................................................................................................................... 87
Figure 41: DDR2 Power-Up and Initialization ................................................................................................. 89
Figure 42: Example: Meeting
Figure 43: Multibank Activate Restriction ....................................................................................................... 93
Figure 44: READ Latency ............................................................................................................................... 95
Figure 45: Consecutive READ Bursts .............................................................................................................. 96
Figure 46: Nonconsecutive READ Bursts ........................................................................................................ 97
Figure 47: READ Interrupted by READ ........................................................................................................... 98
Figure 48: READ-to-WRITE ............................................................................................................................ 98
Figure 49: READ-to-PRECHARGE – BL = 4 ...................................................................................................... 99
Figure 50: READ-to-PRECHARGE – BL = 8 ...................................................................................................... 99
PDF: 09005aef821ae8bf
Rev. O 9/08 EN
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DH ..................................................................................................................... 67
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RRD (MIN) and
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RCD (MIN) .............................................................................. 92
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR2 SDRAM
© 2004 Micron Technology, Inc. All rights reserved.