XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet
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DS610 October 4, 2010 Module 1: Introduction and Ordering Information DS610 (v3.0) October 4, 2010 • Introduction • Features • Architectural Overview • Configuration Overview • General I/O Capabilities • Supported Packages and Package Marking • Ordering Information Module 2: ...
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... DSP processing industry. The Spartan-3A DSP FPGAs extend and enhance the Spartan-3A FPGA family. The XC3SD1800A and the XC3SD3400A devices are tailored for DSP applications and have additional block RAM and XtremeDSP DSP48A slices. The XtremeDSP DSP48A slices replace the 18x18 multipliers found in the Spartan-3A devices and are based on the DSP48 blocks found in the Virtex® ...
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... Notes: 1. The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48A columns of the columns in the selected device, as shown in the diagram above. ...
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... Device DNA identifier useful for tracking purposes, anti-cloning designs protection. Table 2: Available User I/Os and Differential (Diff) I/O Pairs Device XC3SD1800A XC3SD3400A Notes: 1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins ...
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... The Pb-free packages include a ‘G’ character in the ordering code. Example: Device Type Speed Grade Package Type Device Speed Grade XC3SD1800A -4 Standard Performance CS484/ (1) XC3SD3400A -5 High Performance Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range. 2. The low-power option (LI) is exclusively available in the CS(G)484 package and industrial temperature range. ...
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Revision History The following table shows the revision history for this document. Date Version 04/02/07 1.0 Initial Xilinx release. 05/25/07 1.0.1 Minor edits. 06/18/07 1.2 Updated for Production release. 07/16/07 2.0 Added Low-power options. 06/02/08 2.1 Added reference to SCD ...
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DS610 (v3.0) October 4, 2010 Spartan-3A DSP FPGA Design Documentation The functionality of the Spartan®-3A DSP FPGA family is described in the following documents. The topics covered in each guide are listed. • DS706: Extended Spartan-3A Family Overview • UG331: ...
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Revision History The following table shows the revision history for this document. Date Version 04/02/07 1.0 Initial Xilinx release. 05/25/07 1.0.1 Minor edits. 06/18/07 1.2 Updated for Production release. 07/16/07 2.0 Added Low-power options; no changes to this module. 06/02/08 ...
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DS610 (v3.0) October 4, 2010 DC Electrical Characteristics In this section, specifications may be designated as Advance, Preliminary, or Production. These terms are defined as follows: Advance: Initial estimates are based on simulation, early characterization, and/or extrapolation from the characteristics ...
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Power Supply Specifications Table 4: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes and V supplies to ...
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General Recommended Operating Conditions Table 7: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (3) V Input voltage IN T Input signal ...
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General DC Characteristics for I/O Pins Table 8: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description (2) I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins, FPGA powered I Leakage current on pins ...
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... Device Power Typical XC3SD1800A C XC3SD3400A C XC3SD1800A C,I 0.4 LI 0.2 XC3SD3400A C,I 0.4 LI 0.2 XC3SD1800A C XC3SD3400A C Table 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, a design CCAUX Spartan-3A DSP FPGA XPower Estimator www.xilinx.com Commercial Industrial (2) (2) Maximum Maximum ...
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Single-Ended I/O Standards Table 10: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V IOSTANDARD CCO Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 LVCMOS18 1.65 LVCMOS15 1.4 LVCMOS12 1.1 (6) PCI33_3 3.0 (6) ...
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Table 11: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions IOSTANDARD Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – –16 ...
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Differential I/O Standards Differential Input Pairs X-Ref Target - Figure 3 Internal Logic GND level Table 12: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V IOSTANDARD Attribute Min (V) (3) LVDS_25 2.25 (3) LVDS_33 3.0 (4) BLVDS_25 ...
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Differential Output Pairs X-Ref Target - Figure 4 Internal Logic V OUTN V OUTP GND level Table 13: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute Min (mV) LVDS_25 247 LVDS_33 247 BLVDS_25 240 MINI_LVDS_25 300 MINI_LVDS_33 ...
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External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards X-Ref Target - Figure 3. 2.5V CCO CCO LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33 PPDS_25 a) Input-only differential pairs or pairs ...
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... Xilinx static timing analyzer (TRACE in the Xilinx development software) and back-annotated to the simulation netlist. Table 15: Spartan-3A DSP v1.32 Speed Grade Designations Device Advance XC3SD1800A XC3SD3400A Table 16 provides the recent history of the Spartan-3A DSP FPGA speed files. Table 16: Spartan-3A DSP Speed File Version History ISE ...
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... Conditions Device (2) LVCMOS25 , 12 mA XC3SD1800A output drive, Fast slew XC3SD3400A (3) rate, with DCM (2) LVCMOS25 , 12 mA XC3SD1800A output drive, Fast slew XC3SD3400A rate, without DCM Table 26 and are based on the operating conditions set forth in www.xilinx.com Speed Grade -5 -4 Units Max Max 3.28 3 ...
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... DCM (2) LVCMOS25 , XC3SD1800A IFD_DELAY_VALUE = 6, XC3SD3400A without DCM (3) LVCMOS25 , XC3SD1800A IFD_DELAY_VALUE = 0, XC3SD3400A (4) with DCM (3) LVCMOS25 , XC3SD1800A IFD_DELAY_VALUE = 6, XC3SD3400A without DCM Table 26 and are based on the operating conditions set forth in Table Table www.xilinx.com Speed Grade -5 -4 Units Max Max 2.65 3.11 ns 2.25 2 ...
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... XC3SD1800A 2.09 2.24 ns 2.67 2.83 ns 3.25 3.64 ns 3.75 4.20 ns 3.69 4.16 ns 4.47 5.09 ns 5.27 6.02 ns 5.79 6.63 ns XC3SD3400A 2.07 2.44 ns 2.57 3.02 ns 3.44 3.81 ns 4.01 4.39 ns 3.89 4.26 ns 4.43 5.08 ns 5.20 5.95 ns 5.70 6.55 ns XC3SD1800A –0.63 –0.52 ns XC3SD3400A –0.56 –0. ...
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... LVCMOS25 – Table 26 22. Table 22. When the hold time is negative possible to change the data before the clock’s active Max 30879 www.xilinx.com Speed -5 Device Min 1 XC3SD1800A –1.40 –1.40 2 –2.11 –2.11 3 –2.48 –2.48 4 –2.77 –2.77 5 –2.62 –2.62 6 –3.06 –3.06 7 –3.42 –3.42 8 –3.65 –3.65 1 XC3SD3400A – ...
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... Speed Grade Device Units -5 -4 Max Max XC3SD1800A 0.51 0.53 ns XC3SD3400A 0.73 0.93 ns XC3SD1800A 1.29 1.62 ns 1.67 2.08 ns 1.92 2.36 ns 2.38 2.89 ns 2.61 3.17 ns 2.98 3.55 ns 3.30 3.92 ns 3.63 4.37 ns 3.31 4.02 ns 3.69 4.47 ns 3.94 4.77 ns 4.41 5.27 ns 4.67 5. ...
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... Table 26 and are based on the operating conditions set forth in Table 22. www.xilinx.com Speed Grade Device Units -5 -4 Max Max XC3SD1800A 1.79 2.04 ns XC3SD3400A 1.65 2.11 ns XC3SD1800A 2.23 2.47 ns 2.81 3.06 ns 3.39 3.86 ns 3.89 4.43 ns 3.83 4.39 ns 4.61 5.32 ns 5.40 6.24 ns 5.93 6 ...
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Input Timing Adjustments Table 22: Input Timing Adjustments by IOSTANDARD Add the Convert Input Time from Adjustment Below LVCMOS25 to the Following Signal Standard Speed Grade (IOSTANDARD) -5 Single-Ended Standards LVTTL 0.62 LVCMOS33 0.54 LVCMOS25 0.00 LVCMOS18 0.83 LVCMOS15 0.60 ...
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Output Propagation Times Table 23: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output IOCKP Flip-Flop (OFF), the time from the active transition at the OCLK input to data appearing at the Output ...
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Three-State Output Propagation Times Table 24: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK IOCKHZ input of the Three-state Flip-Flop (TFF) to when the Output pin enters ...
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Output Timing Adjustments Table 25: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...
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Table 25: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow ...
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Table 25: Output Timing Adjustments for IOB Convert Output Time from LVCMOS25 with 12mA Drive and Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS12 Slow Fast ...
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Timing Measurement Methodology When measuring timing parameters at the programmable I/Os, different signal standards call for different test conditions. Table 26 lists the conditions to use for each standard. The method for measuring Input timing is as follows: A signal ...
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Table 26: Test Methods for Timing Measurement at I/Os (Cont’d) Signal Standard (IOSTANDARD) V REF Differential LVDS_25 – LVDS_33 – BLVDS_25 – MINI_LVDS_25 – MINI_LVDS_33 – LVPECL_25 – LVPECL_33 – RSDS_25 – RSDS_33 – TMDS_33 – PPDS_25 – PPDS_33 – ...
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... FPGAs mounted in sockets, due to the lead inductance introduced by the socket. (Table 25) to The SSO values assume that the V 3.3V. Setting V characteristics. Table 27: Equivalent V Device XC3SD1800A XC3SD3400A CCO www.xilinx.com and Table 28 provide the essential SSO /GND pairs. The CCO Table 28 ...
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Table 28: Recommended Simultaneously Switching Outputs per V /GND Pair (V CCO CCAUX Signal Standard (IOSTANDARD) Top, Bottom (Banks 0, 2) Single-Ended Standards LVTTL Slow Fast ...
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Table 28: Recommended Simultaneously Switching Outputs per V /GND Pair (V CCO CCAUX Signal Standard (IOSTANDARD) Top, Bottom (Banks 0, 2) LVCMOS25 Slow Fast QuietIO 2 ...
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Table 28: Recommended Simultaneously Switching Outputs per V /GND Pair (V CCO CCAUX Signal Standard (IOSTANDARD) Top, Bottom (Banks 0, 2) LVCMOS12 Slow Fast QuietIO PCI33_3 PCI66_3 HSTL_I HSTL_III HSTL_I_18 HSTL_II_18 ...
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Configurable Logic Block (CLB) Timing Table 29: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time CKO from the active transition at the CLK input to data appearing at the XQ (YQ) output ...
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Table 30: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on SHCKO the distributed RAM output Setup Times T Setup time of data at the BX or ...
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Clock Buffer/Multiplexer Switching Characteristics Table 32: Clock Distribution Switching Characteristics Symbol T Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to GIO O-output delay T Global clock multiplexer (BUFGMUX) select S-input setup to I0 and GSI I1 inputs. Same as ...
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Block RAM Timing Table 33: Block RAM Timing Symbol Clock-to-Output Times T When reading from block RAM, the delay from the active transition at RCKO_DOA_NC the CLK input to data appearing at the DOUT output T Clock CLK to DOUT ...
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DSP48A Timing To reference the DSP48A block diagram, see UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGA User Guide. Table 34: Setup Times for the DSP48A Symbol Description Setup Times of Data/Control Pins to the Input Register Clock T A input ...
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Table 35: Clock to Out, Propagation Delays, and Maximum Frequency for the DSP48A Symbol Description Clock to Out from Output Register Clock to Output Pin T CLK (PREG output DSPCKO_PP Clock to Out from Pipeline Register Clock to ...
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Digital Clock Manager (DCM) Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. ...
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Table 37: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV Frequency for the CLKDV ...
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Table 37: Switching Characteristics for the DLL (Cont’d) Symbol Delay Lines (5) DCM_DELAY_STEP Finest delay resolution, averaged over all steps Notes: 1. The numbers in this table are based on the operating conditions set forth in 2. Indicates the maximum ...
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Table 39: Switching Characteristics for the DFS Symbol Output Frequency Ranges (2) CLKOUT_FREQ_FX Frequency for the CLKFX and CLKFX180 outputs (3)(4) Output Clock Jitter CLKOUT_PER_JITT_FX Period jitter at the CLKFX and CLKFX180 outputs. (5)(6) Duty Cycle CLKOUT_DUTY_CYCLE_ Duty cycle precision ...
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Phase Shifter (PS) Table 40: Recommended Operating Conditions for the PS in Variable Phase Mode Symbol Operating Frequency Ranges PSCLK_FREQ Frequency for the PSCLK input (FPSCLK) Input Pulse Requirements PSCLK_PULSE PSCLK pulse width as a percentage of the PSCLK period ...
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DNA Port Timing Table 43: DNA_PORT Interface Timing Symbol T Setup time on SHIFT before the rising edge of CLK DNASSU T Hold time on SHIFT after the rising edge of CLK DNASH T Setup time on DIN before the ...
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Suspend Mode Timing X-Ref Target - Figure 9 Entering Suspend Mode SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPGA Outputs FPGA Inputs, Interconnect Table 44: Suspend Mode Timing Parameters Symbol Entering Suspend Mode T Rising edge of SUSPEND ...
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Configuration and JTAG Timing General Configuration Power-On/Reconfigure Timing X-Ref Target - Figure 10 V CCINT (Supply) V CCAUX (Supply) V Bank 2 CCO (Supply) PROG_B (Input) INIT_B (Open-Drain) CCLK (Output) Notes: 1. The and V CCINT ...
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Configuration Clock (CCLK) Characteristics Table 46: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T ConfigRate setting CCLK1 T CCLK3 T CCLK6 T CCLK7 T CCLK8 T CCLK10 T CCLK12 T CCLK13 T ...
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Table 47: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol Description Equivalent CCLK clock frequency F by ConfigRate setting CCLK1 F CCLK3 F CCLK6 F CCLK7 F CCLK8 F CCLK10 F CCLK12 F CCLK13 F CCLK17 F CCLK22 ...
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Master Serial and Slave Serial Mode Timing X-Ref Target - Figure 11 PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 11: Waveforms for Master Serial and Slave Serial Configuration Table 50: Timing for the Master Serial and ...
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Slave Parallel Mode Timing X-Ref Target - Figure 12 PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) Notes possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, ...
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Serial Peripheral Interface (SPI) Configuration Timing X-Ref Target - Figure 13 PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK ...
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Table 53: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH T ...
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Byte Peripheral Interface (BPI) Configuration Timing X-Ref Target - Figure 14 PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) M[2:0] <0:1:0> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B CCLK ...
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Table 55: Configuration Timing Requirements for Attached Parallel NOR BPI Flash Symbol Description T Parallel NOR Flash PROM chip-select time ELQV T Parallel NOR Flash PROM output-enable time GLQV T Parallel NOR Flash PROM ...
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IEEE 1149.1/1532 JTAG Test Access Port Timing X-Ref Target - Figure 15 TCK (Input) TMS (Input) TDI (Input) TDO (Output) (2) Table 56: Timing for the JTAG Symbol Clock-to-Output Times T The time from the falling transition on the TCK ...
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Revision History The following table shows the revision history for this document. Date Version 04/02/07 1.0 Initial Xilinx release. 05/25/07 1.0.1 Minor edits. 06/18/07 1.2 Updated for v1.29 production speed files. Noted banking rules in DIFF_HSTL_I and DIFF_HSTL_III to in ...
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DS610 (v3.0) October 4, 2010 Introduction This section describes how the various pins on a Spartan®-3A DSP FPGA connect within the supported component packages and provides device-specific thermal characteristics. For general information on the pin functions and the package characteristics, ...
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... Table 59: Maximum User I/O by Package Maximum Package Device User I/Os and Input-Only XC3SD1800A 309 CS484 XC3SD3400A 309 XC3SD1800A 519 FG676 XC3SD3400A 469 Notes: 1. Some VREFs are on INPUT pins. See pinout tables for details. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions ...
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Electronic versions of the package pinout tables and foot- prints are available for download from the Xilinx® website. Using a spreadsheet program, the data can be sorted and reformatted according to any specific needs. Similarly, the ASCII-text file is easily ...
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... Table 62: Spartan-3A DSP FPGA Package Thermal Characteristics Junction-to-Case Package Device CS484 XC3SD1800A CSG484 XC3SD3400A FG676 XC3SD1800A FGG676 XC3SD3400A DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions XPower Power Estimator Table 62 ) indicates the difference between the temperature measured on the package ...
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... CS484: 484-Ball Chip-Scale Ball Grid Array The 484-ball chip-scale ball grid array, CS484, supports both the XC3SD1800A and XC3SD3400A FPGAs. There are no pinout differences between the two devices. Table 63 lists all the CS484 package pins. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table ...
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Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) Bank Pin Name 0 IO_L19P_0/GCLK8 0 IO_L17N_0/GCLK5 0 IP_0 0 IO_L13N_0 0 IO_L13P_0 0 IO_L05N_0 0 IO_L04N_0 0 IO_L23P_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 0 VCCO_0 1 IO_L02N_1/LDC0 ...
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Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) Bank Pin Name 1 IO_L03N_1/A1 1 IP_L08P_1 1 IO_L03P_1/A0 1 IP_L04N_1/VREF_1 1 IP_L04P_1 1 IO_L06P_1 1 IO_L02P_1/LDC1 1 IO_L06N_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 1 VCCO_1 2 IO_L01P_2/M1 ...
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Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) Bank Pin Name 2 IP_2/VREF_2 2 IO_L24N_2/D3 2 IO_L29N_2 2 IO_L29P_2 2 IO_L26P_2/D2 2 IO_L26N_2/D1 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IP_L39N_3/VREF_3 3 IO_L02N_3 3 IO_L02P_3 ...
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Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) Bank Pin Name 3 IO_L36P_3 3 IO_L35N_3 3 IO_L37N_3 3 IO_L37P_3 3 IO_L35P_3 3 IP_L39P_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 3 VCCO_3 GND GND GND GND GND GND ...
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Table 63: Spartan-3A DSP CS484 Pinout (Cont’d) Bank Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCCAUX SUSPEND VCCAUX PROG_B VCCAUX DONE ...
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... TOTAL Notes VREF are on INPUT pins. Footprint Migration Differences There are no migration footprint differences between the XC3SD1800A and the XC3SD3400A in the CS484 package. DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions All Possible I/O Pins by Type and ...
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CS484 Footprint Left Half of Package (Top View) I/O: Unrestricted, 156 general-purpose user I/O. INPUT: Unrestricted, general-purpose input pin. 41 DUAL: Configuration 51 pins, then possible user I/O. VREF: User I/O or input 28 voltage reference for bank. CLK: User ...
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Bank I/O I/O I/O I/O INPUT INPUT L06P_0 L11P_0 L10P_0 L06N_0 VREF_0 I/O I/O I/O GND GND VCCO_0 L11N_0 L10N_0 L03P_0 I/O I/O I/O I/O I/O INPUT L12N_0 L14N_0 L14P_0 L08N_0 L03N_0 VREF_0 ...
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... XC3SD1800A FPGA Table 66 lists all the FG676 package pins for the XC3SD1800A FPGA. They are sorted by bank number and then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier ...
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... B12 I/O 0 B13 GCLK 0 B14 GCLK 0 B15 I/O 0 B17 I/O 0 B18 I/O 0 B19 I/O 0 B20 VREF 0 www.xilinx.com FG676 XC3SD1800A Pin Name Ball IO_L09N_0 B21 IO_L07P_0 B23 IO_L51P_0 A3 IO_L45P_0 A4 IP_0 A7 IO_L38P_0 A8 IO_L36P_0 A9 IO_L33P_0 A10 IO_L29P_0 A12 IP_0 A13 IO_L26N_0/GCLK7 A14 IO_L23N_0 A15 ...
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... T23 DUAL 1 T24 DUAL 1 R17 DUAL 1 R18 DUAL 1 R19 I/O 1 R20 I/O 1 R21 DUAL 1 www.xilinx.com FG676 XC3SD1800A Pin Name Ball IO_L25N_1/A3 R22 IP_L28P_1/VREF_1 R23 IP_L28N_1 R24 IO_L29P_1/A8 R25 IO_L29N_1/A9 R26 IO_L34P_1/IRDY1/RHCLK6 P18 IO_L30N_1/RHCLK1 P20 IO_L30P_1/RHCLK0 P21 IO_L37P_1 P22 IO_L33P_1/RHCLK4 P23 IO_L31N_1/TRDY1/RHCLK3 ...
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... C25 DUAL 2 C26 DUAL 2 B26 VREF 2 AE26 DUAL 2 AD25 DUAL 2 AD26 I/O 2 AC23 DUAL 2 www.xilinx.com FG676 XC3SD1800A Pin Name Ball IO_L03N_1/A1 AC24 IO_L05N_1 AC25 IO_L06P_1 AC26 IO_L07P_1 AB23 IO_L07N_1/VREF_1 AB24 IO_L06N_1 AB26 IO_L09P_1 AA22 IO_L09N_1 AA23 IO_L11P_1 AA24 IO_L11N_1 AA25 IP_L16P_1 ...
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... AE4 I/O 2 AE6 I/O 2 AE7 I/O 2 AE8 I/O 2 AE9 DUAL 2 AE10 DUAL 2 AE12 DUAL 2 www.xilinx.com FG676 XC3SD1800A Pin Name Ball IO_L26N_2/GCLK15 AE13 IO_L28N_2/GCLK3 AE14 IO_L32N_2/DOUT AE15 IO_L33P_2 AE17 IO_L36N_2/D1 AE18 IO_L37N_2 AE19 IO_L39N_2 AE20 IO_L44P_2 AE21 IO_L48N_2 AE23 IO_L52N_2/CCLK AE24 IO_L51N_2 ...
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... Y8 INPUT 3 Y11 INPUT 3 Y18 INPUT 3 Y19 VREF 3 W18 INPUT 3 AA8 INPUT 3 W11 VCCO 3 W16 VCCO 3 www.xilinx.com FG676 XC3SD1800A Pin Name Ball VCCO_2 AE5 VCCO_2 AE11 VCCO_2 AE16 VCCO_2 AE22 VCCO_2 AB8 VCCO_2 AB14 VCCO_2 AB19 IO_L53P_3 Y1 IO_L53N_3 Y2 IP_L54P_3 Y3 IO_L57P_3 Y5 IO_L57N_3 Y6 IP_L50P_3 ...
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... LHCLK 3 N9 LHCLK 3 M1 VREF I/O 3 M10 I I I/O 3 www.xilinx.com FG676 XC3SD1800A Pin Name Ball IO_L18N_3 L7 IO_L15N_3 L9 IO_L15P_3 L10 IP_L24N_3 K1 IO_L23N_3 K2 IO_L23P_3 K3 IO_L22N_3 K4 IO_L22P_3 K5 IO_L18P_3 K6 IO_L13P_3 K7 IO_L05N_3 K8 IO_L05P_3 K9 IP_L24P_3 J1 IP_L20N_3/VREF_3 J2 IP_L20P_3 J3 IO_L19N_3 J4 IO_L19P_3 J5 IO_L13N_3 J6 IO_L10P_3 J7 IO_L01P_3 J8 IO_L01N_3 ...
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... GND W19 GND GND W24 GND GND V3 GND GND U10 GND GND U13 GND GND U17 GND GND www.xilinx.com FG676 XC3SD1800A Pin Name Ball GND T1 GND T6 GND T12 GND T14 GND T16 GND T21 GND T26 GND R11 GND R13 GND ...
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... AB21 CONFIG VCCINT A2 CONFIG VCCINT G7 JTAG VCCINT E23 JTAG VCCINT D4 JTAG A25 JTAG V9 VCCAUX U14 VCCAUX www.xilinx.com FG676 XC3SD1800A Pin Name Ball VCCAUX T22 VCCAUX P17 VCCAUX N10 VCCAUX L5 VCCAUX K13 VCCAUX J18 VCCAUX E5 VCCAUX E16 VCCAUX E22 VCCAUX AB5 VCCAUX ...
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... User I/Os by Bank Table 67 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The AWAKE pin is counted as a dual-purpose I/O. Table 67: User I/Os Per Bank for the XC3SD1800A in the FG676 Package Maximum I/Os Package I/O Bank ...
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... XC3SD3400A device. Please see the Footprint Migration Differences section for more information. Figure 16: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Left Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions ...
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... I/O INPUT INPUT I/O I/O GND L28P_2 L36P_2 VREF_2 VREF_2 L37P_2 L39P_2 GCLK2 D2 Bank 2 Figure 17: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Right Half) DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions INPUT INPUT I/O A GND ...
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... An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at: www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip. Pinout Table Note: The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices. Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA Bank ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name 0 IO_L10N_0 0 IO_L05P_0 0 IO_L06P_0 0 IO_L44P_0 0 IO_L41N_0 0 IO_L42N_0 0 IO_L40P_0 0 IO_L34P_0 0 IO_L32P_0 0 IO_L30N_0 0 IO_L28N_0/GCLK11 0 IO_L22N_0 0 IO_L21N_0 ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name 1 IO_L12N_1 1 IO_L12P_1 1 IO_L10N_1 1 IO_L14P_1 1 IO_L21N_1 1 IO_L23P_1 1 IO_L23N_1/VREF_1 1 IP_1/VREF_1 1 IO_L17N_1 1 IO_L17P_1 1 IO_L14N_1 1 IO_L26P_1/A4 1 IO_L26N_1/A5 ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name 1 IP_1/VREF_1 1 IO_L58P_1/VREF_1 1 IO_L56N_1 1 IO_L54N_1 1 IO_L54P_1 1 IO_L56P_1 1 IO_L60P_1 1 IO_L61N_1 1 IO_L61P_1 1 IO_L60N_1 1 IO_L63N_1/A23 1 IO_L63P_1/A22 1 IP_1/VREF_1 ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name 2 IO_L48P_2 2 IO_L52P_2/D0/DIN/MISO 2 IO_L51P_2 2 IO_L06P_2 2 IO_L07P_2 2 IO_L10N_2 2 IO_L11N_2 2 IO_L18P_2 2 IO_L19P_2/VS1 2 IO_L22P_2/D7 2 IO_L24N_2/D4 2 IO_L26N_2/GCLK15 2 IO_L28N_2/GCLK3 ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name 2 VCCO_2 2 VCCO_2 2 VCCO_2 3 IO_L53P_3 3 IO_L53N_3 3 IP_3 3 IO_L57P_3 3 IO_L57N_3 3 IP_L50P_3 3 IP_L50N_3/VREF_3 3 IO_L52P_3 3 IO_L52N_3 3 IO_L63N_3 ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name 3 IO_L23N_3 3 IO_L23P_3 3 IO_L22N_3 3 IO_L22P_3 3 IO_L18P_3 3 IO_L13P_3 3 IO_L05N_3 3 IO_L05P_3 3 IP_L24P_3 3 IP_L20N_3/VREF_3 3 IP_L20P_3 3 IO_L19N_3 3 IO_L19P_3 ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND ...
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Table 68: Spartan-3A DSP FG676 Pinout for XC3SD3400A FPGA (Cont’d) Bank XC3SD3400A Pin Name GND GND GND GND VCCAUX SUSPEND VCCAUX DONE VCCAUX PROG_B VCCAUX TDI VCCAUX TDO VCCAUX TMS VCCAUX TCK VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX ...
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User I/Os by Bank Table 69 indicates how the available user-I/O pins are distributed between the four I/O banks on the FG676 package. The AWAKE pin is counted as a dual-purpose I/O. Table 69: User I/Os Per Bank for the ...
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... VCCAUX: Auxiliary supply voltage. 24 Note: The boxes with question marks inside indicate pin differences from the XC3SD1800A device. Please see the Footprint Migration Differences section for more information. Figure 17: FG676 Package Footprint for XC3SD3400A FPGA (Top View–Left Half) DS610 (v3.0) October 4, 2010 ...
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Bank I/O I/O I/O I/O I/O INPUT GND L26N_0 L23N_0 L18N_0 L15N_0 L14N_0 GCLK7 I/O I/O I/O I/O I/O I/O VCCO_0 L26P_0 L14P_0 L23P_0 L19N_0 L18P_0 L15P_0 GCLK6 VREF_0 I/O I/O I/O ...
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... Footprint Migration Differences There are multiple migration footprint differences between the XC3SD1800A and the XC3SD3400A in the FG676 package. These migration footprint differences are shown in FG676 package to a Spartan-3A DSP device in the FG676 package is also possible. The XC3S1800A pin migration differences have been added to ...
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... AA5 IP_L58N_3/ VREF_3 Migration Recommendations There are multiple pinout differences between the XC3SD1800A and the XC3SD3400A FPGAs in the FG676 package. Please note the differences between the two devices from DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions ...
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... DS610 (v3.0) October 4, 2010 Product Specification Spartan-3A DSP FPGA Family: Pinout Descriptions Revision Table 59, Table 63, Table 64, Table (Table 70). Updated FG676 package footprints for XC3SD1800A (Figure 16) and XC3SD3400A FPGA (Figure Package Overview section. Updated Thermal Characteristics in Table 63. Updated links. www.xilinx.com 65, Table 66, ...