XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 51

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 10
Table 45: Power-On Timing and the Beginning of Configuration
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
3.
4.
T
T
T
T
T
POR
PROG
PL
INIT
ICCK
(2)
The numbers in this table are based on the operating conditions set forth in
and V
Power-on reset and the clearing of configuration memory occurs during this period.
This specification applies only to the Master Serial, SPI, and BPI modes.
For details on configuration, see
(2)
Notes:
1.
2.
3.
Symbol
(3)
V
(Open-Drain)
CCO
CCAUX
The V
The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
PROG_B
(Supply)
V
(Supply)
(Supply)
V
(Output)
CCAUX
Bank 2
(Input)
INIT_B
CCINT
CCLK
CCINT
lines.
, V
The time from the application of V
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
The width of the low-going pulse on the PROG_B pin
The time from the rising edge of the PROG_B pin to the
rising transition on the INIT_B pin
Minimum Low pulse width on INIT_B output
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the CCLK
output pin
CCAUX
Figure 10: Waveforms for Power-On and the Beginning of Configuration
, and V
UG332
CCO
supplies can be applied in any order.
Spartan-3 Generation Configuration User Guide.
1.0V
2.0V
2.0V
Description
CCINT
T
T
POR
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
PROG
www.xilinx.com
, V
CCAUX
, and V
T
PL
Table
CCO
7. This means power must be applied to all V
T
ICCK
Device
All
All
All
All
All
All Speed Grades
Min
300
0.5
0.5
–
–
DS529-3_01_052708
Max
18
–
2
–
4
1.2V
3.3V
2.5V
3.3V
2.5V
or
or
CCINT
Units
ms
ms
, V
µs
ns
µs
CCO
51
,