XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 57

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XC3SD1800A-4CS484I

Manufacturer Part Number
XC3SD1800A-4CS484I
Description
FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
Manufacturer
Xilinx Inc
Datasheet

Specifications of XC3SD1800A-4CS484I

Package
484LCSBGA
Family Name
Spartan®-3A
Device Logic Units
37440
Device System Gates
1800000
Maximum Internal Frequency
667 MHz
Typical Operating Supply Voltage
1.2 V
Maximum Number Of User I/os
309
Ram Bits
1548288

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0
Table 53: Configuration Timing Requirements for Attached SPI Serial Flash
DS610 (v3.0) October 4, 2010
Product Specification
Notes:
1.
2.
T
T
T
T
f
C
CCS
DSU
DH
V
Symbol
or f
These requirements are for successful FPGA configuration in SPI mode, where the FPGA generates the CCLK signal. The
post-configuration timing can be different to support the specific needs of the application loaded into the FPGA.
Subtract additional printed circuit board routing delay as required by the application.
R
SPI serial Flash PROM chip-select time
SPI serial Flash PROM data input setup time
SPI serial Flash PROM data input hold time
SPI serial Flash PROM data clock-to-output time
Maximum SPI serial Flash PROM clock frequency (also depends on
specific read command used)
Description
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
T
T
T
CCS
DSU
V
T
f
C
DH
Requirement
T
MCCLn
-------------------------------- -
T
T
T
CCLKn min
MCCL1
MCCL1
T
MCCH1
1
(
T
DCC
T
T
)
CCO
CCO
Units
MHz
ns
ns
ns
ns
57

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