XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 85

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

FG676 Footprint
XC3SD1800A FPGA
Left Half of Package
(Top View)
Note:
inside indicate pin differences from
the XC3SD3400A device. Please
see the
Differences
information.
DS610 (v3.0) October 4, 2010
Product Specification
314
82
51
39
32
77
36
23
14
2
4
2
I/O:
general-purpose user I/O.
INPUT:
general-purpose input pin.
DUAL:
then possible user I/O.
VREF:
voltage reference for bank.
CLK:
clock buffer input.
CONFIG:
configuration pins
JTAG:
port pins.
SUSPEND:
SUSPEND and
dual-purpose AWAKE
Power Management pins
GND:
VCCO:
supply for bank.
VCCINT:
supply voltage (+1.2V).
VCCAUX:
supply voltage.
Footprint Migration
The boxes with triangles
Unrestricted,
section for more
User I/O, input, or
Ground
Dedicated JTAG
Configuration pins,
User I/O or input
Output voltage
Unrestricted,
Internal core
Dedicated
Auxiliary
Dedicated
Figure 16: FG676 Package Footprint for XC3SD1800A FPGA (Top View–Left Half)
.
–
W
A
B
C
D
G
H
K
M
N
R
U
A
A
A
B
A
C
A
D
A
A
E
F
J
L
P
T
V
Y
E
F
VREF_3
VREF_3
LHCLK2
VREF_3
L02N_3
L04N_3
INPUT
L08N_3
L11P_3
INPUT
L16N_3
L17N_3
INPUT
L24P_3
INPUT
L24N_3
L29N_3
L31P_3
L33P_3
L36P_3
L44P_3
L47P_3
INPUT
L50P_3
L53P_3
L60P_3
L60N_3
L65P_3
INPUT
L66P_3
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INPUT
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
1
PROG_
VCCO_3
VREF_3
VCCO_3
VCCO_3
VREF_3
VCCO_3
VREF_3
INPUT
INPUT
INPUT
INPUT
LHCLK3
L47N_3
INPUT
L50N_3
L53N_3
L65N_3
INPUT
L66N_3
INPUT
L02P_3
L04P_3
L08P_3
L11N_3
L16P_3
L17P_3
L20N_3
L23N_3
L29P_3
L31N_3
L33N_3
L36N_3
L44N_3
L55P_3
L64P_3
IRDY2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
∇
2
B
LHCLK5
INPUT
INPUT
L51P_0
L51N_0
L06P_3
L07P_3
L14N_3
L14P_3
INPUT
L20P_3
L23P_3
L25N_3
L27N_3
L34N_3
L37P_3
L38P_3
INPUT
L46P_3
L52P_3
L54P_3
L55N_3
L62P_3
L64N_3
L06P_2
L06N_2
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
3
Spartan-3A DSP FPGA Family: Pinout Descriptions
VREF_3
LHCLK4
L45N_0
INPUT
L06N_3
L07N_3
L09N_3
L12N_3
L19N_3
L22N_3
L30N_3
L37N_3
L38N_3
L42N_3
INPUT
L46N_3
L52N_3
INPUT
L54N_3
INPUT
L58P_3
INPUT
L62N_3
L01P_2
L01N_2
L07P_2
L07N_2
L45P_0
INPUT
L25P_3
L27P_3
L34P_3
TMS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
∇
∇
M1
M0
∇
4
VCCAUX
VCCAUX
VCCAUX
VCCO_0
VCCO_3
VCCO_3
VCCO_3
VREF_3
VCCO_2
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
L44P_0
L09P_3
L12P_3
L19P_3
L22P_3
L28P_3
L30P_3
L40P_3
L42P_3
L49P_3
L49N_3
L57P_3
L58N_3
L10P_2
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
I/O
∇
∇
∇
∇
5
LHCLK0
INPUT
VREF_2
L41P_0
L41N_0
L44N_0
INPUT
L03P_3
L10N_3
L13N_3
L18P_3
L28N_3
L32P_3
L39N_3
L40N_3
L51N_3
L59N_3
L63N_3
L57N_3
L08P_2
L08N_2
L10N_2
GND
GND
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
6
VREF_0
LHCLK1
INPUT
INPUT
L02N_2
L14N_2
INPUT
L11N_2
INPUT
L42P_0
L42N_0
L48N_0
L48P_0
L03N_3
L10P_3
L13P_3
L18N_3
L26N_3
L32N_3
L39P_3
L45N_3
L51P_3
L56P_3
L59P_3
L63P_3
L02P_2
CSO_B
L11P_2
TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
M2
∇
∇
7
Bank 2
Bank 0
VCCO_0
PUDC_B
VCCO_3
VCCO_3
VCCO_2
VREF_0
INPUT
INPUT
L38P_0
L38N_0
L40P_0
L40N_0
L52P_0
L52N_0
L01P_3
L05N_3
L26P_3
L41P_3
L45P_3
L56N_3
L61N_3
L14P_2
L18P_2
L18N_2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
8
VCCAUX
LHCLK6
VREF_2
L36P_0
L36N_0
L37N_0
INPUT
INPUT
L47P_0
L47N_0
L01N_3
L05P_3
L15N_3
L21N_3
L35P_3
L41N_3
L43N_3
L48N_3
L61P_3
L05P_2
L05N_2
INPUT
L15P_2
L15N_2
INPUT
L19P_2
L19N_2
TRDY2
GND
VS1
VS0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
∇
9
VCCAUX
LHCLK7
VREF_3
VREF_2
VREF_2
INPUT
INPUT
L09N_2
L12N_2
INPUT
INPUT
INPUT
L22N_2
L33P_0
L33N_0
L34P_0
L34N_0
L37P_0
L46P_0
L46N_0
L15P_3
L21P_3
L35N_3
L43P_3
L48P_3
L09P_2
L12P_2
L22P_2
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
10
I/O
I/O
I/O
I/O
I/O
∇
I/O
I/O
I/O
I/O
I/O
I/O
∇
D7
D6
VCCINT
VCCINT
VCCINT
VCCAUX
VCCO_0
VCCO_0
VCCO_2
VCCO_2
VREF_0
INPUT
INPUT
VREF_0
INPUT
L32P_0
L32N_0
L43P_0
L43N_0
L13N_2
L13P_2
L23N_2
L23P_2
GND
GND
GND
GND
GND
GND
GND
11
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
∇
VCCINT
VCCINT VCCINT
VCCINT
VCCINT
RDWR_B
VREF_2
L29P_0
L29N_0
L30N_0
INPUT
L31P_0
L31N_0
L35P_0
L35N_0
L39P_0
L39N_0
L16P_2
L16N_2
L17P_2
L17N_2
L21P_2
L21N_2
INPUT
L24N_2
L24P_2
GND
GND
GND
VS2
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
D4
D5
VCCINT
VCCINT
VCCINT
VCCAUX
GCLK10
GCLK11
VCCO_0
GCLK13
GCLK12
GCLK15
GCLK14
INPUT
INPUT
INPUT
L20N_2
L25N_2
INPUT
INPUT
L26N_2
L28P_0
L28N_0
L30P_0
L27P_0
GCLK8
L27N_0
GCLK9
L20P_2
L25P_2
L26P_2
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
13
I/O
I/O
I/O
85