XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 37

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

Table 28: Recommended Simultaneously Switching
Outputs per V
DS610 (v3.0) October 4, 2010
Product Specification
LVCMOS12
PCI33_3
PCI66_3
HSTL_I
HSTL_III
HSTL_I_18
HSTL_II_18
HSTL_III_18
SSTL18_I
SSTL18_II
SSTL2_I
SSTL2_II
SSTL3_I
SSTL3_II
Signal Standard
(IOSTANDARD)
CCO
QuietIO
/GND Pair (V
Slow
Fast
2
4
6
2
4
6
2
4
6
CCAUX
Top, Bottom
(Banks 0, 2)
40
31
55
16
17
10
18
–
–
–
–
–
–
–
–
–
–
7
–
–
8
6
CS484, FG676
Package Type
= 3.3V) (Cont’d)
Left, Right
(Banks 1, 3)
40
25
18
31
13
55
36
36
16
13
20
17
15
18
10
9
8
5
8
9
9
7
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Table 28: Recommended Simultaneously Switching
Outputs per V
Notes:
1.
2.
3.
Differential Standards (Number of I/O Pairs or Channels)
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Not all I/O standards are supported on all I/O banks. The left and
right banks (I/O banks 1 and 3) support higher output drive
current than the top and bottom banks (I/O banks 0 and 2).
Similarly, true differential output standards, such as LVDS,
RSDS, PPDS, miniLVDS, and TMDS, are only supported in top
or bottom banks (I/O banks 0 and 2). Refer to UG331: Spartan-3
Generation FPGA User Guide for additional information.
The numbers in this table are recommendations that assume
sound board lay out practice. This table assumes the following
parasitic factors: combined PCB trace and land inductance per
V
Test limits are the V
standard.
If more than one signal standard is assigned to the I/Os of a
given bank, refer to XAPP689: Managing Ground Bounce in
Large FPGAs for information on how to perform weighted
average SSO calculations.
CCO
Signal Standard
(IOSTANDARD)
and GND pin of 1.0 nH, receiver capacitive load of 15 pF.
CCO
/GND Pair (V
IL
/V
IH
voltage limits for the respective I/O
CCAUX
Top, Bottom
(Banks 0, 2)
22
27
22
27
22
27
27
22
27
4
8
–
5
–
–
3
–
9
–
4
3
CS484, FG676
Package Type
= 3.3V) (Cont’d)
Inputs Only
Inputs Only
Left, Right
(Banks 1, 3)
10
–
–
4
–
–
–
–
–
–
–
8
2
4
4
7
4
9
4
5
3
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