XC3SD1800A-4CS484I Xilinx Inc, XC3SD1800A-4CS484I Datasheet - Page 58

• Manufacturer Part Number: XC3SD1800A-4CS484I
• Description: FPGA Spartan®-3A Family 1.8M Gates 37440 Cells 667MHz 90nm Technology 1.2V 484-Pin LCSBGA
• Manufacturer: Xilinx Inc

Specifications of XC3SD1800A-4CS484I

• Package: 484LCSBGA
• Family Name: Spartan®-3A
• Device Logic Units: 37440
• Device System Gates: 1800000
• Maximum Internal Frequency: 667 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 309
• Ram Bits: 1548288

Byte Peripheral Interface (BPI) Configuration Timing
X-Ref Target - Figure 14
(Open-Drain)
Table 54: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode
DS610 (v3.0) October 4, 2010
Product Specification
T
T
T
T
T
T
T
T
CCLK1
CCLKn
MINIT
INITM
INITADDR
CCO
DCC
CCD
Symbol
PROG_B
LDC[2:0]
PUDC_B
CSO_B
A[25:0]
INIT_B
(Input)
(Input)
(Input)
(Input)
M[2:0]
D[7:0]
CCLK
HDC
Shaded values indicate specifications on attached parallel NOR Flash PROM.
Initial CCLK clock period
CCLK clock period after FPGA loads ConfigRate setting
Setup time on M[2:0] mode pins before the rising edge of INIT_B
Hold time on M[2:0] mode pins after the rising edge of INIT_B
Minimum period of initial A[25:0] address cycle; LDC[2:0] and HDC are asserted
and valid
Address A[25:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK rising edge
Hold time on D[7:0] data inputs after CCLK rising edge
Figure 14: Waveforms for Byte-wide Peripheral Interface (BPI) Configuration
T
MINIT
<0:1:0>
PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process.
T
INITM
Pin initially pulled High by internal pull-up resistor if PUDC_B input is Low.
Pin initially high-impedance (Hi-Z) if PUDC_B input is High.
Description
000_0000
T
CCLK1
Byte 0
Spartan-3A DSP FPGA Family: DC and Switching Characteristics
www.xilinx.com
Mode input pins M[2:0] are sampled when INIT_B goes High. After this point,
input values do not matter until DONE goes High, at which point the mode pins
become user-I/O pins.
T
INITADDR
000_0001
Byte 1
T
AVQV
Data
New ConfigRate active
Minimum
T
CCLK1
Address
T
50
CCO
0
0
5
Data
See T
T
DCC
See
See
See
SMDCC
T
Address
CCLKn
Maximum
Table 46
Table 46
Table 50
Data
in
–
–
5
–
Table 51
Address
DS529-3_05_090610
T
Data
CCD
T
cycles
Units
CCLK1
ns
ns
ns
58