AD5383BST-3 Analog Devices Inc, AD5383BST-3 Datasheet - Page 30

• Manufacturer Part Number: AD5383BST-3
• Description: IC DAC 12BIT 32CH 3V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5383BST-3

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015)
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 39mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5383
2-Byte Mode
Following initialization of 2-byte mode, the user can
sequentially update channels. The device address byte is only
required once, and the address pointer is configured for auto-
increment or burst mode.
The user must begin with an address byte (R/ W = 0), after
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte is followed by a specific
pointer byte (0xFF) that initiates the burst mode of operation.
The address pointer initializes to Channel 0, the data following
the pointer is loaded to Channel 0, and the address pointer
automatically increments to the next address.
The REG0 and REG1 bits in the data byte determine which
register is updated. In this mode, following the initializa-tion,
only the two data bytes are required to update a channel. The
channel address automatically increments from Address 0 to
Channel 31 and then returns to the normal 3-byte mode of
operation. This mode allows transmission of data to all
channels in one block and reduces the software overhead in
configuring all channels. A STOP condition at any time exits
this mode. Toggle mode is not supported in 2-byte mode.
Figure 33 shows a typical configuration.
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
START COND
BY MASTER
REG1
REG1
1
REG1
REG0
REG0
0
MOST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE
REG0
MOST SIGNIFICANT DATA BYTE
ADDRESS BYTE
MSB
MSB
1
MSB
0
1
AD1
AD0
CHANNEL N DATA FOLLOWED BY STOP
Figure 33. 2-Byte, I
CONVERTER
LSB
LSB
ACK BY
R/W
CONVERTER
LSB
Rev. B | Page 30 of 40
ACK BY
ACK BY
AD538x
CHANNEL 0 DATA
CHANNEL 1 DATA
CONVERTER
ACK BY
A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1
MSB
MSB
MSB
2
C Write Operation
MSB
PARALLEL INTERFACE
The SER/ PAR pin must be tied low to enable the parallel
interface and disable the serial interfaces.
timing diagram for a parallel write. The parallel interface is
controlled by the following pins:
CS Pin
Active low device select pin.
WR Pin
On the rising edge of WR , with CS low, the addresses on
Pin A4 to Pin A0 are latched; data present on the data bus is
loaded into the selected input registers.
REG0, REG1 Pins
The REG0 and REG1 pins determine the destination register
of the data being written to the AD5383. See Table 11.
Pins A4 to A0
Each of the 32 DAC channels can be addressed individually.
Pins DB11 to DB0
The AD5383 accepts a straight 12-bit parallel word on DB11
to DB0, where DB11 is the MSB and DB0 is the LSB.
LEAST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
POINTER BYTE
CONVERTER
LSB
LSB
CONVERTER
ACK BY
ACK BY
AD538x
ACK BY
Figure 7
CONVERTER
LSB
ACK BY
shows the
MASTER
COND
STOP
BY