AD5383BST-3 Analog Devices Inc, AD5383BST-3 Datasheet - Page 32

• Manufacturer Part Number: AD5383BST-3
• Description: IC DAC 12BIT 32CH 3V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5383BST-3

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015)
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 39mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5383
AD5383 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit = 0. This is done by
writing to the synchronous serial port control register (SSPCON).
See the PIC16/17 Microcontroller User Manual. In this example
I/O, Port RA1 is being used to pulse SYNC and enable the serial
port of the AD5383. This microcontroller transfers only eight
bits of data during each serial transfer operation; therefore,
three consecutive read/write operations may be needed
depending on the mode.
diagram.
AD5383 to 8051
The AD5383 requires a clock synchronized to the serial data.
Therefore, the 8051 serial interface must be operated in Mode 0.
In this mode, serial data enters and exits through RxD, and a
shift clock is output on TxD. Figure 37 shows how the 8051 is
connected to the AD5383. Because the AD5383 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5383
requires its data to be MSB first. Since the 8051 outputs the LSB
first, the transmit routine must take this into account.
PIC16C6X/7X
SDO/RC5
SCK/RC3
SDI/RC4
RA1
Figure 36. AD5383-to-PIC16C6x/7x Interface
Figure 36
shows the connection
DV
DD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5383
2
C
Rev. B | Page 32 of 40
AD5383 to ADSP-2101/ADSP-2103
Figure 38 shows a serial interface between the AD5383 and the
ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should
be set up to operate in SPORT transmit alternate framing mode.
The ADSP-2101/ADSP-2103 SPORT is programmed through
the SPORT control register and should be configured as follows:
internal clock operation, active low framing, and 16-bit word
length. Transmission is initiated by writing a word to the Tx
register after the SPORT has been enabled.
ADSP-2101/
ADSP-2103
8XC51
Figure 38. AD5383-to-ADSP-2101/ADSP-2103 Interface
P1.1
SCK
RxD
RFS
TxD
TFS
DR
DT
Figure 37. AD5383-to-8051 Interface
DV
DV
DD
DD
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
SER/PAR
RESET
SDO
DIN
SCLK
SYNC
SPI/I
AD5383
AD5383
2
2
C
C