AD5383BST-3 Analog Devices Inc, AD5383BST-3 Datasheet - Page 8

• Manufacturer Part Number: AD5383BST-3
• Description: IC DAC 12BIT 32CH 3V 100-LQFP
• Manufacturer: Analog Devices Inc

Specifications of AD5383BST-3

• Design Resources: 32 Channels of Programmable Voltage with Excellent Temperature Drift Performance Using AD5383 (CN0014) AD5383 Channel Monitor Function (CN0015)
• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: Serial, Parallel
• Number Of Converters: 32
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 39mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD5383
TIMING CHARACTERISTICS
SERIAL INTERFACE TIMING
DV
noted.
Table 6.
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
1
2
3
4
5
6
7
7A
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Guaranteed by design and characterization, not production tested.
All input signals are specified with t
See Figure 2, Figure 3, Figure 4, and Figure 5.
Standalone mode only.
Daisy-chain mode only.
4
4
4
4
5
5
5
DD
= 2.7 V to 5.5 V; AV
1, 2, 3
Limit at T
33
13
13
13
13
33
10
50
5
4.5
30
670
20
20
100
0
100
8
20
35
20
5
8
20
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T
r
MIN
= t
, T
f
= 5 ns (10% to 90% of V
MAX
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns min
μs typ
ns min
μs max
ns max
ns min
ns min
ns min
TO OUTPUT PIN
Figure 2. Load Circuit for SDO Timing Diagram
CC
(Serial Interface, Daisy-Chain Mode)
) and are timed from a voltage level of 1.2 V.
Rev. B | Page 8 of 40
C
50pF
L
200μA
200μA
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in readback mode
Data setup time
Data hold time
24th SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time, boost mode off
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
I
I
OL
OH
V
V
OH
OL
(MAX)
(MIN) OR
MIN
to T
MAX
, unless otherwise