EPM7256AETC100-5N Altera, EPM7256AETC100-5N Datasheet - Page 18

• Manufacturer Part Number: EPM7256AETC100-5N
• Description: IC MAX 7000 CPLD 256 100-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7256AETC100-5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 84
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000A
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 250MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 84
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MAX 7000A Programmable Logic Device Data Sheet
18
Programming Times
The time required to implement each of the six programming stages can
be broken into the following two elements:
By combining the pulse and shift times for each of the programming
stages, the program or verify time can be derived as a function of the TCK
frequency, the number of devices, and specific target device(s). Because
different ISP-capable devices have a different number of EEPROM cells,
both the total fixed and total variable times are unique for a single device.
Programming a Single MAX 7000A Device
The time required to program a single MAX 7000A device in-system can
be calculated from the following formula:
where: t
The ISP times for a stand-alone verification of a single MAX 7000A device
can be calculated from the following formula:
where: t
t
t
PROG
VER
A pulse time to erase, program, or read the EEPROM cells.
A shifting time based on the test clock (TCK) frequency and the
number of TCK cycles to shift instructions, address, and data into the
device.
=
=
t
VPULSE
t
Cycle
f
t
Cycle
TCK
t
PROG
PPULSE
VER
VPULSE
PPULSE
PTCK
VTCK
+
+
Cycle VTCK
--------------------------------
Cycle
------------------------------- -
= Programming time
= Sum of the fixed times to erase, program, and
= Number of TCK cycles to program a device
= TCK frequency
f TCK
= Verify time
= Sum of the fixed times to verify the EEPROM cells
= Number of TCK cycles to verify a device
f
TCK
verify the EEPROM cells
PTCK
Altera Corporation