EPM7256AETC100-5N Altera, EPM7256AETC100-5N Datasheet - Page 23

• Manufacturer Part Number: EPM7256AETC100-5N
• Description: IC MAX 7000 CPLD 256 100-TQFP
• Manufacturer: Altera
• Series: MAX® 7000Ar

Specifications of EPM7256AETC100-5N

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 5.5ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 16
• Number Of Macrocells: 256
• Number Of Gates: 5000
• Number Of I /o: 84
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: EEPROM
• Number Of Logic Elements/cells: 16
• Family Name: MAX 7000A
• # Macrocells: 256
• Number Of Usable Gates: 5000
• Frequency (max): 250MHz
• Propagation Delay Time: 5.5ns
• Number Of Logic Blocks/elements: 16
• # I/os (max): 84
• Operating Supply Voltage (typ): 3.3V
• In System Programmable: Yes
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
Figure 8
Figure 8. MAX 7000A JTAG Waveforms
Table 11
devices.
Note:
(1)
Captured
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Table 11. JTAG Timing Parameters & Values for MAX 7000A Devices
JCP
JCH
JCL
JPSU
JPH
JPCO
JPZX
JPXZ
JSSU
JSH
JSCO
JSZX
JSXZ
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
Timing parameters shown in this table apply for all specified VCCIO levels.
TDI
shows timing information for the JTAG signals.
shows the JTAG timing parameters and values for MAX 7000A
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
MAX 7000A Programmable Logic Device Data Sheet
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Min
100
50
50
20
45
20
45
t
Max
JPXZ
25
25
25
25
25
25
Note (1)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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