EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 14
EP1AGX20CF484C6N
Manufacturer Part Number
EP1AGX20CF484C6N
Description
IC ARRIA GX FPGA 20K 484FBGA
Manufacturer
Altera
Series
Arria GXr
Datasheet
1.EP1AGX20CF484C6N.pdf
(234 pages)
Specifications of EP1AGX20CF484C6N
Number Of Logic Elements/cells
21580
Number Of Labs/clbs
1079
Total Ram Bits
1229184
Number Of I /o
230
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Arria™ GX
Number Of Logic Blocks/elements
21580
# I/os (max)
230
Process Technology
CMOS
Operating Supply Voltage (typ)
1.2V
Logic Cells
21580
Ram Bits
1229184
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
21580
Family Type
Arria GX
No. Of I/o's
230
Operating Frequency Max
622.08MHz
Operating Temperature Range
0°C To +85°C
Logic Case Style
BGA
No. Of Pins
484
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2395
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1AGX20CF484C6N
Manufacturer:
ALTERA
Quantity:
672
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2–8
Arria GX Device Handbook, Volume 1
f
Figure 2–7
Figure 2–7. Serializer
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at
rates up to 3.125 Gbps. The common mode voltage (V
set to 600 or 700 mV.
For more information about the Arria GX transceiver buffers, refer to the
Transceiver Architecture
The output buffer, as shown in
serializer and consists of a programmable output driver, a programmable
pre-emphasis circuit, and OCT circuitry.
shows the serializer block diagram.
Local Clock
Central /
Divider
From 8B/10B
CMU
Encoder
High-speed serial clock
Low-speed parallel clock
10
chapter.
Figure
2–8, is directly driven by the high-speed data
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CM
) of the output driver may be
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
To Transmitter
Output Buffer
Arria GX
Transceivers
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