EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 91

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–70. Signal Path Through the I/O Block
Figure 2–71. Control Signal Selection per IOE
Notes to
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection
© December 2009 Altera Corporation
multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives
the control selection multiplexers.
Figure
Dedicated I/O
Clock [7..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
From Logic
To Logic
2–71:
Array
Array
Row or Column
Figure 2–70
Each IOE contains its own control signal selection for the following control signals:
oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out.
Figure 2–71
io_dataouta
io_dataoutb
io_clk[7..0]
io_dataina
io_datainb
io_ce_out
io_ce_in
io_aclr
io_sclr
io_clk
io_oe
io_oe
io_sclr
io_aclr
io_ce_out
io_ce_in
io_clk
shows the signal paths through the I/O block.
shows the control signal selection.
Selection
Control
Signal
(Note 1)
clk_in
oe
ce_in
ce_out
aclr/apreset
sclr/spreset
clk_in
clk_out
clk_out
To Other
IOEs
ce_in
ce_out
IOE
aclr/apreset
Arria GX Device Handbook, Volume 1
sclr/spreset
oe
2–85