EP1AGX20CF484C6N Altera, EP1AGX20CF484C6N Datasheet - Page 30

• Manufacturer Part Number: EP1AGX20CF484C6N
• Description: IC ARRIA GX FPGA 20K 484FBGA
• Manufacturer: Altera
• Series: Arria GXr

Specifications of EP1AGX20CF484C6N

• Number Of Logic Elements/cells: 21580
• Number Of Labs/clbs: 1079
• Total Ram Bits: 1229184
• Number Of I /o: 230
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 484-FBGA
• Family Name: Arria™ GX
• Number Of Logic Blocks/elements: 21580
• # I/os (max): 230
• Process Technology: CMOS
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 21580
• Ram Bits: 1229184
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FC-FBGA
• No. Of Macrocells: 21580
• Family Type: Arria GX
• No. Of I/o's: 230
• Operating Frequency Max: 622.08MHz
• Operating Temperature Range: 0°C To +85°C
• Logic Case Style: BGA
• No. Of Pins: 484
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2395

2–24
Table 2–6. Reset Signal Map to Arria GX Blocks
Calibration Block
Transceiver Clocking
Arria GX Device Handbook, Volume 1
rx_digitalreset
rx_analogreset
tx_digitalreset
gxb_powerdown
gxb_enable
Reset Signal
Table 2–6
circuitry affected by each signal.
Arria GX devices use the calibration block to calibrate OCT for the PLLs, and their
associated output buffers, and the terminating resistors on the transceivers. The
calibration block counters the effects of process, voltage, and temperature (PVT). The
calibration block references a derived voltage across an external reference resistor to
calibrate the OCT resistors on Arria GX devices. You can power down the calibration
block. However, powering down the calibration block during operations can yield
transmit and receive data errors.
This section describes the clock distribution in an Arria GX transceiver channel and
the PLD clock resource utilization by the transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
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lists the reset signals available in Arria GX devices and the transceiver
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© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
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Transceivers
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