XCS05XL-4VQG100C Xilinx Inc, XCS05XL-4VQG100C Datasheet - Page 10

• Manufacturer Part Number: XCS05XL-4VQG100C
• Description: IC SPARTAN-XL FPGA 5K 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS05XL-4VQG100C

• Number Of Logic Elements/cells: 238
• Number Of Labs/clbs: 100
• Total Ram Bits: 3200
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1289

Spartan and Spartan-XL FPGA Families Data Sheet
This high value makes them unsuitable as wired-AND
pull-up resistors.
Table 7: Supported Destinations for Spartan/XL
Outputs
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resistor
active. Alternatively, they can be individually configured with
the pull-down resistor, or as a driven output, or to be driven
by an external source. To activate the internal pull-up, attach
the PULLUP library component to the net attached to the
pad. To activate the internal pull-down, attach the PULL-
DOWN library component to the net attached to the pad.
Set/Reset
As with the CLB registers, the GSR signal can be used to
set or clear the input and output registers, depending on the
value of the INIT attribute or property. The two flip-flops can
be individually configured to set or clear on reset and after
configuration. Other than the global GSR net, no user-con-
trolled set/reset signal is available to the I/O flip-flops
(Figure
tial state of the flip-flop and the response to the GSR pulse.
Independent Clocks
Separate clock signals are provided for the input (IK) and
output (OK) flip-flops. The clock can be independently
inverted for each flip-flop within the IOB, generating either
10
Notes:
1.
Any device,
V
CMOS-threshold
inputs
Any device,
V
TTL-threshold inputs
Any device,
V
CMOS-threshold
inputs
CC
CC
CC
Only if destination device has 5V tolerant inputs.
Destination
= 3.3V,
= 5V,
= 5V,
5). The choice of set or reset applies to both the ini-
3.3V, CMOS
Spartan-XL
Outputs
√
√
Unreliable
Data
TTL
5V,
√
√
Spartan
Outputs
Some
CMOS
5V,
√
√
www.xilinx.com
(1)
falling-edge or rising-edge triggered flip-flops. The clock
inputs for each IOB are independent.
Common Clock Enables
The input and output flip-flops in each IOB have a common
clock enable input (see EC signal in
through configuration, can be activated individually for the
input or output flip-flop, or both. This clock enable operates
exactly like the EC signal on the Spartan/XL FPGA CLB. It
cannot be inverted within the IOB.
Routing Channel Description
All internal routing channels are composed of metal seg-
ments with programmable switching points and switching
matrices to implement the desired routing. A structured,
hierarchical matrix of routing channels is provided to
achieve efficient automated routing.
This section describes the routing channels available in
Spartan/XL devices.
gram of the CLB routing channels. The implementation soft-
ware automatically assigns the appropriate resources
based on the density and timing requirements of the design.
The following description of the routing channels is for infor-
mation only and is simplified with some minor details omit-
ted. For an exact interconnect description the designer
should open a design in the FPGA Editor and review the
actual connections in this tool.
The routing channels will be discussed as follows;
•
•
•
CLB Routing Channels
The routing channels around the CLB are derived from
three types of interconnects; single-length, double-length,
and longlines. At the intersection of each vertical and hori-
zontal routing channel is a signal steering matrix called a
Programmable Switch Matrix (PSM).
basic routing channel configuration showing single-length
lines, double-length lines and longlines as well as the CLBs
and PSMs. The CLB to routing channel interface is shown
as well as how the PSMs interface at the channel intersec-
tions.
CLB routing channels which run along each row and
column of the CLB array.
IOB routing channels which form a ring (called a
VersaRing) around the outside of the CLB array. It
connects the I/O with the CLB routing channels.
Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Figure 8
shows a general block dia-
DS060 (v1.8) June 26, 2008
Product Specification
Figure 8
Figure
shows the
5), which
R