XCS05XL-4VQG100C Xilinx Inc, XCS05XL-4VQG100C Datasheet - Page 34

• Manufacturer Part Number: XCS05XL-4VQG100C
• Description: IC SPARTAN-XL FPGA 5K 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS05XL-4VQG100C

• Number Of Logic Elements/cells: 238
• Number Of Labs/clbs: 100
• Total Ram Bits: 3200
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1289

Spartan and Spartan-XL FPGA Families Data Sheet
Configuration Sequence
There are four major steps in the Spartan/XL FPGA
power-up configuration sequence.
•
•
•
•
The full process is illustrated in
Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When V
passes the write and read test of a sample pair of configu-
ration bits, a time delay is started. This time delay is nomi-
nally 16 ms. The delay is four times as long when in Master
Serial Mode to allow ample time for all slaves to reach a sta-
ble V
mended, the longest delay takes precedence. Therefore,
devices with different time delays can easily be mixed and
matched in a daisy chain.
This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
34
Configuration Memory Clear
Initialization
Configuration
Start-up
CC
. When all INIT pins are tied together, as recom-
CC
reaches an operational level, and the circuit
0
1
LAST DATA FRAME
1
X2
1
Figure
1
2
1
30.
Figure 29: Circuit for Generating CRC-16
3
1
4
0 15 14 13 12 11 10 9
Polynomial: X16 + X15 + X2 + 1
5
Readback Data Stream
6
7
www.xilinx.com
CRC – CHECKSUM
8
9 10 11 12 13 14
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Config-
uration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscil-
lator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is asserted,
the logic initiates one additional clearing of the configuration
frames and then tests the INIT input.
Initialization
During initialization and configuration, user pins HDC, LDC,
INIT and DONE provide status outputs for the system inter-
face. The outputs LDC, INIT and DONE are held Low and
HDC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initializa-
tion pass through the frame addresses. There is a deliber-
ate delay before a Master-mode device recognizes an
inactive INIT. Two internal clocks after the INIT pin is recog-
nized as High, the device samples the MODE pin to deter-
mine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.
8
7 6 5
SERIAL DATA IN
X15
15
DS060 (v1.8) June 26, 2008
DS060_29_080400
X16
Product Specification
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