XCS05XL-4VQG100C Xilinx Inc, XCS05XL-4VQG100C Datasheet - Page 60

• Manufacturer Part Number: XCS05XL-4VQG100C
• Description: IC SPARTAN-XL FPGA 5K 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS05XL-4VQG100C

• Number Of Logic Elements/cells: 238
• Number Of Labs/clbs: 100
• Total Ram Bits: 3200
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1289

Spartan and Spartan-XL FPGA Families Data Sheet
Spartan-XL Family IOB Input Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
60
Notes:
1.
2.
Setup Times
Hold Times
Propagation Delays
Delay Adder for Input with Full Delay Option
Global Set/Reset
Symbol
T
T
T
T
T
T
T
T
T
T
POCK
Delay
MRW
ECIK
PICK
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
IKRI
IKLI
PID
RRI
PLI
Clock Enable (EC) to Clock (IK)
Pad to Clock (IK), no delay
Pad to Fast Capture Latch Enable (OK), no delay
All Hold Times
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
T
T
Minimum GSR pulse width
Delay from GSR input to any Q
PICKD
PDLI
= T
= T
PLI
PICK
+ T
+ T
Delay
Delay
Description
www.xilinx.com
in the Xilinx Development System) and back-annotated to
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
Device
10.5
Min
1.0
0.0
4.0
4.8
5.0
5.5
6.5
0.0
0.7
-
-
-
-
-
-
-
-
-
-5
Speed Grade
Max
10.0
11.0
12.0
0.9
2.1
1.0
1.1
9.0
9.5
-
-
-
-
-
-
-
-
-
-
DS060 (v1.8) June 26, 2008
11.5
Min
0.0
1.2
0.8
0.0
4.7
5.6
5.9
6.5
7.6
-
-
-
-
-
-
-
-
-
Product Specification
-4
Max
10.5
11.0
11.5
12.5
13.5
1.1
2.5
1.1
1.2
-
-
-
-
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
R