XCS05XL-4VQG100C Xilinx Inc, XCS05XL-4VQG100C Datasheet - Page 35

• Manufacturer Part Number: XCS05XL-4VQG100C
• Description: IC SPARTAN-XL FPGA 5K 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS05XL-4VQG100C

• Number Of Logic Elements/cells: 238
• Number Of Labs/clbs: 100
• Total Ram Bits: 3200
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1289

DS060 (v1.8) June 26, 2008
Product Specification
SAMPLE PRELOAD
(* if PROGRAM = High)
SAMPLE/PRELOAD
Figure 30: Power-up Configuration Sequence
SAMPLE/PRELOAD
CONFIGURE*
CONFIGURE
Boundary Scan
READBACK
EXTEST*
BYPASS
Instructions
Available:
BYPASS
BYPASS
EXTEST
USER 1
USER 2
R
Master CCLK
Goes Active
Configuration Memory
F
If Boundary Scan
is Selected
Test MODE, Generate
One Time-Out Pulse
Completely Clear
Data to DOUT
Keep Clearing
Configuration
Configuration
Configuration
Count Equals
Yes
of 16 or 64 ms
Data Frame
Yes
Operational
Once More
Mode Line
Sequence
Load One
Yes
No
Start-Up
Memory
memory
High? if
Sample
Config-
Master
uration
Length
Frame
CCLK
Count
Error
V CC
Valid
Pass
INIT
Full
Yes
Yes
No
No
No
No
Master Delays Before
Sampling Mode Line
~1.3 μs per Frame
Pull INIT Low
and Stop
PROGRAM
= Low
DS060_30_080400
Yes
www.xilinx.com
Configuration
The 0010 preamble code indicates that the following 24 bits
represent the length count for serial modes. The length
count is the total number of configuration clocks needed to
load the complete configuration data. (Four additional con-
figuration clocks are required to complete the configuration
process, as discussed below.) After the preamble and the
length count have been passed through to any device in the
daisy chain, its DOUT is held High to prevent frame start
bits from reaching any daisy-chained devices. In Spar-
tan-XL family Express mode, the length count bits are
ignored, and DOUT is held Low, to disable the next device in
the pseudo daisy chain.
A specific configuration bit, early in the first frame of a mas-
ter device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configura-
tion clock is selected by the bitstream, the slower clock rate
is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configu-
ration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error by
pulling the open-drain INIT pin Low. After all configuration
frames have been loaded into an FPGA using a serial
mode, DOUT again follows the input data so that the
remaining data is passed on to the next device. In
Spartan-XL family Express mode, when the first device is
fully programmed, DOUT goes High to enable the next
device in the chain.
Delaying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply rise
time is excessive or poorly defined. As long as PROGRAM
is Low, the FPGA keeps clearing its configuration memory.
When PROGRAM goes High, the configuration memory is
cleared one more time, followed by the beginning of config-
uration, provided the INIT input is not externally held Low.
Note that a Low on the PROGRAM input automatically
forces a Low on the INIT output. The Spartan/XL FPGA
PROGRAM pin has a permanent weak pull-up.
Avoid holding PROGRAM Low for more than 500 μs. The
500 μs maximum limit is only a recommendation, not a
requirement. The only effect of holding PROGRAM Low for
more than 500 μs is an increase in current, measured at
about 40 mA in the XCS40XL. This increased current can-
not damage the device. This applies only during reconfigu-
ration, not during power-up. The INIT pin can also be held
Low to delay reconfiguration, and the same characteristics
apply as for the PROGRAM pin.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the FPGA
Spartan and Spartan-XL FPGA Families Data Sheet
Figure
30.)
35