XCS05XL-4VQG100C Xilinx Inc, XCS05XL-4VQG100C Datasheet - Page 51

• Manufacturer Part Number: XCS05XL-4VQG100C
• Description: IC SPARTAN-XL FPGA 5K 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-XLr

Specifications of XCS05XL-4VQG100C

• Number Of Logic Elements/cells: 238
• Number Of Labs/clbs: 100
• Total Ram Bits: 3200
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1289

Spartan Family IOB Output Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values. For more
specific, more precise, and worst-case guaranteed data,
use the values reported by the static timing analyzer (TRCE
in the Xilinx Development System) and back-annotated to
DS060 (v1.8) June 26, 2008
Product Specification
Notes:
1.
2.
3.
4.
Clocks
Propagation Delays - TTL Outputs
Setup and Hold Times
Global Set/Reset
Symbol
T
T
T
T
T
T
T
T
T
T
T
OKPOF
OKPOS
T
T
Delay adder for CMOS Outputs option (with fast slew rate option): for -3 speed grade, add 1.0 ns; for -4 speed grade, add 0.8 ns.
Delay adder for CMOS Outputs option (with slow slew rate option): for -3 speed grade, add 2.0 ns; for -4 speed grade, add 1.5 ns.
Output timing is measured at ~50% V
rise/fall times are approximately two times longer than fast output rise/fall times.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
TSONF
TSONS
T
OKEC
T
ECOK
TSHZ
MRW
OOK
OPF
OPS
OKO
RPO
CH
CL
R
Clock High
Clock Low
Clock (OK) to Pad, fast
Clock (OK to Pad, slew-rate limited
Output (O) to Pad, fast
Output (O) to Pad, slew-rate limited
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
3-state to Pad active and valid, slew-rate limited
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
Minimum GSR pulse width
Delay from GSR input to any Pad
Description
(1,2)
CC
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
www.xilinx.com
the simulation netlist. These path delays, provided as a
guideline, have been extracted from the static timing ana-
lyzer report. All timing parameters assume worst-case oper-
ating conditions (supply voltage and junction temperature).
Values are expressed in nanoseconds unless otherwise
noted.
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
All devices
Spartan and Spartan-XL FPGA Families Data Sheet
Device
XCS05
XCS10
XCS20
XCS30
XCS40
11.5
Min
3.0
3.0
2.5
0.0
2.0
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-4
Speed Grade
Max
12.0
12.5
13.0
13.5
14.0
3.3
6.9
3.6
7.2
3.0
6.0
9.6
-
-
-
-
-
-
13.5
Min
4.0
4.0
3.8
0.0
2.7
0.5
-
-
-
-
-
-
-
-
-
-
-
-
-3
Max
15.0
15.7
16.2
16.9
17.5
4.5
7.0
4.8
7.3
3.8
7.3
9.8
-
-
-
-
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
51