EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 233

IC STRATIX FPGA 20K LE 672-FBGA

EP1S20F672I7

Manufacturer Part Number
EP1S20F672I7
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F672I7

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA
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Part Number:
EP1S20F672I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
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Part Number:
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Manufacturer:
ALTERA
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Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
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Part Number:
EP1S20F672I7N
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Quantity:
10 000
Part Number:
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Manufacturer:
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0
Part Number:
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Altera Corporation
January 2006
Notes to
(1)
(2)
(3)
(4)
3.3-V SSTL-3 Class I
2.5-V SSTL-2 Class II
2.5-V SSTL-2 Class I
1.8-V SSTL-18 Class II
1.8-V SSTL-18 Class I
1.5-V HSTL Class II
1.5-V HSTL Class I
1.8-V HSTL Class II
1.8-V HSTL Class I
3.3-V PCI
3.3-V PCI-X 1.0
3.3-V Compact PCI
3.3-V AGP 1X
3.3-V CTT
Table 4–101. Reporting Methodology For Maximum Timing For Single-Ended Output Pins (Part 2 of 2)
Notes
Input measurement point at internal node is 0.5 × V
Output measuring point for data is V
Input stimulus edge rate is 0 to V
The first value is for output rising edge and the second value is for output falling edge. The hyphen (-) indicates
infinite resistance or disconnection.
I/O Standard
(1), (2),
Table
(4)
(4)
4–101:
(3)
(4)
(4)
–/25
–/25
–/25
–/25
R
Ω
UP
CCINT
25/–
25/–
25/–
25/–
R
Ω
MEAS
DN
in 0.5 ns (internal signal) from the driver preceding the IO buffer.
.
Loading and Termination
R
25
25
25
25
25
25
Ω
0
0
0
0
0
0
0
0
S
CCINT
50
25
50
25
50
25
50
25
50
50
R
.
Ω
T
2.950
2.370
2.370
1.650
1.650
1.400
1.400
1.650
1.650
2.950
2.950
2.950
2.950
2.050
V
(V)
CCIO
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
1.250
1.110
1.110
0.760
0.760
0.700
0.700
0.700
0.700
2.950
2.950
2.950
2.950
1.350
VTT
(V)
(pF)
30
30
30
30
30
20
20
20
20
10
10
10
10
30
C
L
Measurement
0.841/1.814
0.841/1.814
0.841/1.814
0.841/1.814
V
1.250
1.110
1.110
0.760
0.760
0.680
0.680
0.880
0.880
1.350
Point
MEAS
4–63

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