EP1S20F672I7 Altera, EP1S20F672I7 Datasheet - Page 261

IC STRATIX FPGA 20K LE 672-FBGA

EP1S20F672I7

Manufacturer Part Number
EP1S20F672I7
Description
IC STRATIX FPGA 20K LE 672-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S20F672I7

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
426
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
426
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA
0
Part Number:
EP1S20F672I7
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S20F672I7B
Manufacturer:
ALTERA
0
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA20
Quantity:
212
Part Number:
EP1S20F672I7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F672I7N
Manufacturer:
ALTERA
0
Part Number:
EP1S20F672I7N
0
Notes to
(1)
(2)
t
t
DUTY
LOCK
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 4 of 4)
Symbol
When J = 4, 7, 8, and 10, the SERDES block is used.
When J = 2 or J = 1, the SERDES is bypassed.
Table
4–125:
LVDS (J = 2
through 10)
LVDS (J =1)
and LVPECL,
PCML,
HyperTransport
technology
All
Conditions
47.5
Min
45
-5 Speed Grade
Typ
50
50
Max
52.5
100
55
47.5
Min
45
-6 Speed Grade
Typ
50
50
Max
52.5
100
55
Notes
47.5
Min
45
(1),
-7 Speed Grade
(2)
Typ
50
50
Max
52.5
100
55
47.5
Min
45
-8 Speed Grade
Typ
50
50
Max
52.5
100
55
Unit
μs
%
%

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