XA3S700A-4FGG400I Xilinx Inc, XA3S700A-4FGG400I Datasheet - Page 37

• Manufacturer Part Number: XA3S700A-4FGG400I
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400I

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Buffer/Multiplexer Switching Characteristics
Table 32: Clock Distribution Switching Characteristics
18 x 18 Embedded Multiplier Timing
Table 33: 18 x 18 Embedded Multiplier Timing
DS681 (v1.1) February 3, 2009
Product Specification
Notes:
The numbers in this table are based on the operating conditions set forth in
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1
inputs. Same as BUFGCE enable CE-input
Frequency of signals distributed on global buffers (all sides)
Combinatorial Delay
T
Clock-to-Output Times
T
T
T
Setup Times
T
T
T
Hold Times
T
T
T
MULT
MSCKP_P
MSCKP_A
MSCKP_B
MSDCK_P
MSDCK_A
MSDCK_B
MSCKD_P
MSCKD_A
MSCKD_B
Symbol
R
Combinational multiplier propagation delay from the A and B inputs to the P outputs,
assuming 18-bit inputs and a 36-bit product (AREG, BREG, and PREG registers
unused)
Clock-to-output delay from the active transition of the CLK input to valid data appearing
on the P outputs when using the PREG register
Clock-to-output delay from the active transition of the CLK input to valid data appearing
on the P outputs when using either the AREG or BREG register
Data setup time at the A or B input before the active transition at the CLK when using
only the PREG output register (AREG, BREG registers unused)
Data setup time at the A input before the active transition at the CLK when using the
AREG input register
Data setup time at the B input before the active transition at the CLK when using the
BREG input register
Data hold time at the A or B input after the active transition at the CLK when using only
the PREG output register (AREG, BREG registers unused)
Data hold time at the A input after the active transition at the CLK when using the AREG
input register
Data hold time at the B input after the active transition at the CLK when using the BREG
input register
(4)
(4)
Description
(4)
(4)
Description
www.xilinx.com
(2,3)
Table
(3)
8.
Symbol
F
T
T
BUFG
(2,4)
(3)
GIO
GSI
Minimum
–
–
0
Speed Grade
3.98
0.00
0.00
0.00
0.45
0.45
Min
Speed Grade
Maximum
–
–
–
0.23
0.63
333
-4
-4
Max
4.88
1.30
4.97
–
–
–
–
–
–
Units
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
37