XA3S700A-4FGG400Q Xilinx Inc, XA3S700A-4FGG400Q Datasheet
XA3S700A-4FGG400Q
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XA3S700A-4FGG400Q Summary of contents
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R DS681 (v1.1) February 3, 2009 Summary The Xilinx Automotive (XA) Spartan solves the design challenges in most high-volume, cost-sensitive, I/O-intensive automotive electronics applications. The four-member family offers densities ranging from 200,000 to 1.4 million system gates, as shown in ...
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... RAM blocks. Each block RAM is associated with a dedicated multiplier. The DCMs are positioned in the center with two at the top and two at the bottom of the device. The XA3S700A and XA3S1400A add two DCMs in the middle of the two columns of block RAM and multipliers. The XA Spartan-3A family features a rich network of routing that interconnect all five functional elements, transmitting signals among them ...
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... CLBs DCM IOBs Notes: 1. The XA3S700A and XA3S1400A have two additional DCMs on both the left and right sides as indicated by the dashed lines. Configuration XA Spartan-3A FPGAs are programmed by loading configuration data into robust, reprogrammable, static CMOS configuration latches (CCLs) that collectively control all functional elements and routing resources. The FPGA’ ...
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... XA3S200A (35) (50) 195 90 XA3S400A (35) (50) XA3S700A - - XA3S1400A - - Notes: 1. The number shown in bold indicates the maximum number of I/O and input-only pins. The number shown in (italics) indicates the number of input-only pins. The differential (Diff) input-only pin count includes both differential pairs on input-only pins and differential pairs on I/O pins within I/O banks that are restricted to differential inputs ...
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... Table 3: XA Spartan-3A FPGA Family Production Status (Production Speed File) Temperature Range Speed Grade XA3S200A XA3S400A XA3S700A XA3S1400A Package Marking Figure 2 shows the top marking for Spartan-3A FPGAs in BGA packages. The markings for the BGA packages are nearly identical to those for the quad-flat packages, except that the marking is rotated with respect to the ball A1 indicator. ...
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... Device Speed Grade XA3S200A –4 Standard Performance XA3S400A XA3S700A XA3S1400A Notes: 1. The XA Spartan-3A FPGA product line is available in -4 Speed Grade only. DC Electrical Characteristics All parameter limits are representative of worst-case supply voltage and junction temperature conditions. Unless otherwise noted, the published parameter values apply ...
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R Power Supply Specifications Table 5: Supply Voltage Thresholds for Power-On Reset Symbol V Threshold for the V CCINTT V Threshold for the V CCAUXT V Threshold for the V CCO2T Notes and V supplies ...
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General Recommended Operating Conditions Table 8: General Recommended Operating Conditions Symbol T Junction temperature J V Internal supply voltage CCINT (1) V Output driver supply voltage CCO V Auxiliary supply voltage CCAUX (2) V Input voltage IN T Input signal ...
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R General DC Characteristics for I/O Pins Table 9: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins Symbol Description I Leakage current at User I/O, L Input-only, Dual-Purpose, and Dedicated pins, FPGA powered I Leakage current on pins ...
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... XA3S400A 0.3 XA3S700A 0.3 XA3S1400A 0.3 XA3S200A XA3S400A XA3S700A XA3S1400A Table 8. = 3.6V, and V = 3.6V. The FPGA is programmed with a “blank” configuration data file (that is, CCO CCAUX provides quick, approximate, typical estimates, and does not require a netlist of the design. b) XPower www.xilinx.com ...
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R Single-Ended I/O Standards Table 11: Recommended Operating Conditions for User I/Os Using Single-Ended Standards V for Drivers CCO IOSTANDARD Attribute Min (V) Nom (V) LVTTL 3.0 (4) LVCMOS33 3.0 (4,5) LVCMOS25 2.3 (4) LVCMOS18 1.65 (4) LVCMOS15 1.4 (4) ...
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Table 12: DC Characteristics of User I/Os Using Single-Ended Standards Test Conditions I I IOSTANDARD OL OH Attribute (mA) (mA) (3) LVTTL 2 2 – – – – – –16 ...
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R Differential I/O Standards Differential Input Pairs Internal Logic V V GND level Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards V CCO IOSTANDARD Attribute Min (V) (3) LVDS_25 2.25 (3) LVDS_33 3.0 (4) BLVDS_25 2.25 ...
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Differential Output Pairs Internal Logic V OUTN V OUTP GND level Table 14: DC Characteristics of User I/Os Using Differential Signal Standards IOSTANDARD Attribute Min (mV) LVDS_25 247 LVDS_33 247 BLVDS_25 240 MINI_LVDS_25 300 MINI_LVDS_33 300 RSDS_25 100 RSDS_33 100 ...
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R External Termination Requirements for Differential I/O LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards 2.5V CCO CCO LVDS_33, LVDS_25, MINI_LVDS_33, MINI_LVDS_25, RSDS_33, RSDS_25, PPDS_33 PPDS_25 a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint ...
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... Table 16: XA Spartan-3A FPGA v1.41 Speed Grade Designations Device Production – XA3S200A 4 – XA3S400A 4 – XA3S700A 4 – XA3S1400A 4 Table 17 provides the recent history of the XA Spartan-3A FPGA speed files. Table 17: XA Spartan-3A FPGA Speed File Version History ISE Version Release 1 ...
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... XA3S200A output drive, Fast slew XA3S400A (3) rate, with DCM XA3S700A XA3S1400A (2) LVCMOS25 , 12mA XA3S200A output drive, Fast slew XA3S400A rate, without DCM XA3S700A XA3S1400A Table 26 and are based on the operating conditions set forth in Table www.xilinx.com Speed Grade -4 Max Units 3. ...
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... DCM XA3S700A XA3S1400A (3) LVCMOS25 , XA3S200A IFD_DELAY_VALUE = 5, XA3S400A without DCM XA3S700A XA3S1400A Table 26 and are based on the operating conditions set forth in Table 22. If this is true of the data Input, add the Table 22. If this is true of the data Input, subtract the www.xilinx.com R Speed Grade ...
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... Input Flip-Flop (IFF). The Input Delay is programmed. DS681 (v1.1) February 3, 2009 Product Specification IFD_ DELAY_ Conditions VALUE Device (2) LVCMOS25 0 XA3S200A XA3S400A XA3S700A XA3S1400A (2) LVCMOS25 1 XA3S200A XA3S400A XA3S700A XA3S1400A www.xilinx.com Speed Grade -4 Min Units 1.81 ns 1.51 ns 1.51 ns 1.74 ns 2.20 ns 2.93 ns 3. ...
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... Input Flip-Flop (IFF) to the point where data must be held at the Input pin. The Input Delay is programmed. 20 IFD_ DELAY_ Conditions VALUE Device (2) LVCMOS25 0 XA3S200A XA3S400A XA3S700A XA3S1400A (2) LVCMOS25 1 XA3S200A XA3S400A XA3S700A XA3S1400A www.xilinx.com R Speed Grade -4 Min Units –0.65 ns –0.42 ns –0.67 ns –0.71 ns –1.51 ns –2.09 ns –2.40 ns – ...
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... When the hold time is negative possible to change the data before the clock’s active DELAY_ Conditions VALUE (2) LVCMOS25 www.xilinx.com Speed Grade IFD_ -4 DELAY_ VALUE Device Min All 1.61 and are based on the operating conditions set forth in Speed Grade IFD_ -4 Device Max 0 XA3S200A 2.04 XA3S400A 1.74 XA3S700A 1.74 XA3S1400A 1.97 Units ns Units ...
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... Units XA3S200A 2.43 ns 3.16 ns 4.01 ns 4.60 ns 4.43 ns 5.46 ns 6.33 ns 6.94 ns XA3S400A 2.25 ns 2.90 ns 3.66 ns 4.19 ns 4.18 ns 5.03 ns 5.88 ns 6.42 ns XA3S700A 2.18 ns 3.06 ns 3.95 ns 4.54 ns 4.37 ns 5.42 ns 6.33 ns 6.96 ns XA3S1400A 2.40 ns 3.15 ns 3.99 ns 4.55 ns 4.42 ns 5.32 ns 6.21 ns 6.80 ns DS681 (v1.1) February 3, 2009 ...
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R Input Timing Adjustments Table 22: Input Timing Adjustments by IOSTANDARD Add the Adjustment Below Convert Input Time from LVCMOS25 to the Following Speed Grade Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 LVCMOS12 PCI33_3 HSTL_I HSTL_III HSTL_I_18 ...
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Output Propagation Times Table 23: Timing for the IOB Output Path Symbol Description Clock-to-Output Times T When reading from the Output Flip-Flop IOCKP (OFF), the time from the active transition at the OCLK input to data appearing at the Output ...
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R Three-State Output Propagation Times Table 24: Timing for the IOB Three-State Path Symbol Description Synchronous Output Enable/Disable Times T Time from the active transition at the OTCLK input IOCKHZ of the Three-state Flip-Flop (TFF) to when the Output pin ...
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Output Timing Adjustments Table 25: Output Timing Adjustments for IOB Adjustment Convert Output Time from LVCMOS25 with 12mA Drive and Speed Grade Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Single-Ended Standards LVTTL Slow ...
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R Table 25: Output Timing Adjustments for IOB Adjustment Convert Output Time from LVCMOS25 with 12mA Drive and Speed Grade Fast Slew Rate to the Following Signal Standard (IOSTANDARD) LVCMOS25 Slow ...
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Table 25: Output Timing Adjustments for IOB Adjustment Convert Output Time from LVCMOS25 with 12mA Drive and Speed Grade Fast Slew Rate to the Following Signal Standard (IOSTANDARD) Differential Standards LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 LVPECL_33 RSDS_25 RSDS_33 TMDS_33 ...
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R Table 26: Test Methods for Timing Measurement at I/Os Signal Standard (IOSTANDARD) V REF Single-Ended LVTTL - LVCMOS33 - LVCMOS25 - LVCMOS18 - LVCMOS15 - LVCMOS12 - PCI33_3 Rising - Falling HSTL_I 0.75 HSTL_III 0.9 HSTL_I_18 0.9 HSTL_II_18 0.9 ...
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Table 26: Test Methods for Timing Measurement at I/Os (Continued) Signal Standard (IOSTANDARD) V REF DIFF_SSTL18_I 0.9 DIFF_SSTL18_II 0.9 DIFF_SSTL2_I 1.25 DIFF_SSTL2_II 1.25 DIFF_SSTL3_I 1.5 DIFF_SSTL3_II 1.5 Notes: 1. Descriptions of the relevant symbols are as follows: V – The ...
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... Table 27: Equivalent V /GND Pairs per Bank CCO Package Style (Pb-free) Device FTG256 XA3S200A 4 XA3S400A 4 XA3S700A – XA3S1400A – DS681 (v1.1) February 3, 2009 Product Specification Table 27 and Table 28 guidelines. For each device/package combination, provides the number of equivalent V each output signal standard and drive strength, ...
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Table 28: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO (V =3.3V) CCAUX FTG256, FGG400, FGG484 Signal Standard Top, Bottom (IOSTANDARD) (Banks 0,2) Single-Ended Standards LVTTL Slow Fast 2 4 ...
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R Table 28: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO (V =3.3V)(Continued) CCAUX FTG256, FGG400, FGG484 Signal Standard Top, Bottom (IOSTANDARD) (Banks 0,2) LVCMOS25 Slow Fast ...
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Table 28: Recommended Number of Simultaneously Switching Outputs per V -GND Pair CCO (V =3.3V)(Continued) CCAUX FTG256, FGG400, FGG484 Signal Standard Top, Bottom (IOSTANDARD) (Banks 0,2) Differential Standards (Number of I/O Pairs or Channels) LVDS_25 LVDS_33 BLVDS_25 MINI_LVDS_25 MINI_LVDS_33 LVPECL_25 ...
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R Configurable Logic Block (CLB) Timing Table 29: CLB (SLICEM) Timing Symbol Clock-to-Output Times T When reading from the FFX (FFY) Flip-Flop, the time from the active CKO transition at the CLK input to data appearing at the XQ (YQ) ...
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Table 30: CLB Distributed RAM Switching Characteristics Symbol Clock-to-Output Times T Time from the active edge at the CLK input to data appearing on the SHCKO distributed RAM output Setup Times T Setup time of data at the BX or ...
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R Clock Buffer/Multiplexer Switching Characteristics Table 32: Clock Distribution Switching Characteristics Description Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs. Same as BUFGCE enable CE-input ...
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Table 33 Embedded Multiplier Timing (Continued) Symbol Clock Frequency F Internal operating frequency for a two-stage 18x18 multiplier using the AREG and BREG MULT input registers and the PREG output register Notes: 1. Combinational delay is less ...
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R Digital Clock Manager Timing For specification purposes, the DCM consists of three key components: the Delay-Locked Loop (DLL), the Digital Frequency Synthesizer (DFS), and the Phase Shifter (PS). Aspects of DLL operation play a role in all DCM applications. ...
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Table 36: Switching Characteristics for the DLL Symbol Output Frequency Ranges CLKOUT_FREQ_CLK0 Frequency for the CLK0 and CLK180 outputs CLKOUT_FREQ_CLK90 Frequency for the CLK90 and CLK270 outputs CLKOUT_FREQ_2X Frequency for the CLK2X and CLK2X180 outputs CLKOUT_FREQ_DV Frequency for the CLKDV ...
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R Digital Frequency Synthesizer Table 37: Recommended Operating Conditions for the DFS Symbol (2) Input Frequency Ranges F CLKIN_FREQ_FX Frequency for the CLKIN input CLKIN (3) Input Clock Jitter Tolerance CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN input, based on CLKFX ...
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Table 38: Switching Characteristics for the DFS (Continued) Symbol Lock Time (2, 3) LOCK_FX The time from deassertion at the DCM’s Reset input to the rising transition at its LOCKED output. The DFS asserts LOCKED when the CLKFX and CLKFX180 ...
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R Miscellaneous DCM Timing Table 41: Miscellaneous DCM Timing Symbol DCM_RST_PW_MIN Minimum duration of a RST pulse width (2) DCM_RST_PW_MAX Maximum duration of a RST pulse width (3) DCM_CONFIG_LAG_TIME Maximum duration from V configuration successfully completed (DONE pin goes High) ...
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Suspend Mode Timing Entering Suspend Mode SUSPEND Input AWAKE Output Flip-Flops, Block RAM, Distributed RAM FPGA Outputs FPGA Inputs, Interconnect Table 43: Suspend Mode Timing Parameters Symbol Entering Suspend Mode T Rising edge of SUSPEND pin to falling edge of ...
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... V CCINT CCAUX CCO Table www.xilinx.com T ICCK DS529-3_01_112906 -4 Speed Grade Device Min Max All – 18 All 0.5 - XA3S200A – 0.5 XA3S400A – 1 XA3S700A – 2 XA3S1400A – 2 All 250 – All 0 This means power must be applied to all V 1.2V 2.5V or 3.3V Units ms μ μ ...
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Configuration Clock (CCLK) Characteristics Table 45: Master Mode CCLK Output Period by ConfigRate Option Setting Symbol Description CCLK clock period by T CCLK1 ConfigRate setting T CCLK3 T CCLK6 T CCLK7 T CCLK8 T CCLK10 T CCLK12 T CCLK13 T ...
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R Table 46: Master Mode CCLK Output Frequency by ConfigRate Option Setting Symbol Description Equivalent CCLK clock frequency F CCLK1 by ConfigRate setting F CCLK3 F CCLK6 F CCLK7 F CCLK8 F CCLK10 F CCLK12 F CCLK13 F CCLK17 F ...
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Master Serial and Slave Serial Mode Timing PROG_B (Input) INIT_B (Open-Drain) CCLK (Input/Output) DIN (Input) DOUT (Output) Figure 11: Waveforms for Master Serial and Slave Serial Configuration Table 49: Timing for the Master Serial and Slave Serial Configuration Modes Symbol ...
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R Slave Parallel Mode Timing PROG_B (Input) INIT_B (Open-Drain) CSI_B (Input) RDWR_B (Input) CCLK (Input (Inputs) Notes possible to abort configuration by pulling CSI_B Low in a given CCLK cycle, then switching RDWR_B Low ...
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Serial Peripheral Interface Configuration Timing PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) VS[2:0] <1:1:1> (Input) M[2:0] <0:0:1> (Input) T MINIT INIT_B (Open-Drain) CCLK DIN (Input) CSO_B MOSI Pin initially ...
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R Table 52: Configuration Timing Requirements for Attached SPI Serial Flash Symbol T SPI serial Flash PROM chip-select time CCS T SPI serial Flash PROM data input setup time DSU T SPI serial Flash PROM data input hold time DH ...
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Byte Peripheral Interface Configuration Timing PROG_B (Input) PUDC_B PUDC_B must be stable before INIT_B goes High and constant throughout the configuration process. (Input) M[2:0] <0:1:0> (Input) T MINIT INIT_B (Open-Drain) LDC[2:0] HDC CSO_B CCLK A[25:0] D[7:0] (Input) Shaded values indicate ...
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R Table 54: Configuration Timing Requirements for Attached Parallel NOR Flash Symbol Description T Parallel NOR Flash PROM chip-select time ELQV T Parallel NOR Flash PROM output-enable time GLQV T Parallel NOR Flash PROM ...
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... All functions except those shown below Configuration commands (CFG_IN, ISC_PROGRAM) All functions except ISC_DNA command During ISC_DNA command All operations on XA3S200A and XA3S400A FPGAs and for BYPASS or HIGHZ instructions on all FPGAs All operations on XA3S700A and XA3S1400A FPGAs, except for BYPASS or HIGHZ instructions Table 8. www.xilinx.com T ...
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R Revision History The following table shows the revision history for this document. Date Version 04/30/08 1.0 Initial release. 05/07/08 1.0.1 Updated Figure 14, minor edits under Features and Package Marking, Table 20 and 21. • Updated 02/03/09 1.1 • ...
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R DS681 (v1.1) February 3, 2009 Product Specification ...