XA3S700A-4FGG400Q Xilinx Inc, XA3S700A-4FGG400Q Datasheet - Page 54

• Manufacturer Part Number: XA3S700A-4FGG400Q
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400Q

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IEEE 1149.1/1553 JTAG Test Access Port Timing
Table 55: Timing for the JTAG Test Access Port
54
Notes:
1.
Clock-to-Output Times
T
Setup Times
T
T
Hold Times
T
T
Clock Timing
T
T
T
T
F
Symbol
TCKTDO
TDITCK
TMSTCK
TCKTDI
TCKTMS
CCH
CCL
CCHDNA
CCLDNA
TCK
The numbers in this table are based on the operating conditions set forth in
TCK
TMS
TDI
TDO
(Input)
(Input)
(Input)
(Output)
The time from the falling transition on the TCK pin to data appearing at the TDO pin
The time from the setup of data at the
TDI pin to the rising transition at the
TCK pin
The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
The High pulse width at the TCK pin
The Low pulse width at the TCK pin
Frequency of the TCK signal
T
TDITCK
T
TMSTCK
Figure 15: JTAG Waveforms
All functions except ISC_DNA command
All devices and functions except those shown below
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XA3S700A and XA3S1400A FPGAs
All functions except those shown below
Configuration commands (CFG_IN, ISC_PROGRAM)
During ISC_DNA command
All operations on XA3S200A and XA3S400A FPGAs
and for BYPASS or HIGHZ instructions on all FPGAs
All operations on XA3S700A and XA3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
Description
www.xilinx.com
T
TCKTDI
T
TCKTMS
Table
8.
T
TCKTDO
T
CCH
1/F
TCK
DS681 (v1.1) February 3, 2009
T
-4 Speed Grade
CCL
11.0
Min
1.0
7.0
7.0
2.0
10
10
0
0
5
5
0
Product Specification
DS099_06_040703
10,000
10,000
Max
11.0
33
20
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
R