XA3S700A-4FGG400Q Xilinx Inc, XA3S700A-4FGG400Q Datasheet - Page 31

• Manufacturer Part Number: XA3S700A-4FGG400Q
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400Q

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended
maximum allowable number of Simultaneous Switching
Outputs (SSOs). These guidelines describe the maximum
number of user I/O pins of a given output signal standard
that should simultaneously switch in the same direction,
while maintaining a safe level of switching noise. Meeting
these guidelines for the stated test conditions ensures that
the FPGA operates free from the adverse effects of ground
and power bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage
difference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other
variables contribute to SSO noise levels, including stray
inductance on the PCB as well as capacitive loading at
receivers. Any SSO-induced voltage consequently affects
internal switching noise margins and ultimately signal
quality.
Table 27: Equivalent V
DS681 (v1.1) February 3, 2009
Product Specification
XA3S200A
XA3S400A
XA3S700A
XA3S1400A
Device
R
CCO
FTG256
/GND Pairs per Bank
4
4
–
–
Package Style (Pb-free)
FGG400
–
5
5
–
CCO
www.xilinx.com
FGG484
–
–
5
6
Table 27
guidelines. For each device/package combination,
provides the number of equivalent V
each output signal standard and drive strength,
recommends the maximum number of SSOs, switching in
the same direction, allowed per V
I/O bank. The guidelines in
package style, slew rate, and output drive current.
Furthermore, the number of SSOs is specified by I/O bank.
Generally, the left and right I/O banks (Banks 1 and 3)
support higher output drive current.
Multiply the appropriate numbers from
Table 28
allowed within an I/O bank. Exceeding these SSO
guidelines might result in increased power or ground
bounce, degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead
inductance introduced by the socket.
Ball grid array packages are recommended for applications
with a large number of simultaneously switching outputs.
SSO
MAX
and
to calculate the maximum number of SSOs
/IO Bank =
Table 28
provide the essential SSO
Table 27
Table 28
CCO
x
Table 28
CCO
are categorized by
/GND pair within an
Table 27
/GND pairs. For
Table 28
and
Table 27
31