XA3S700A-4FGG400I Xilinx Inc, XA3S700A-4FGG400I Datasheet - Page 40

• Manufacturer Part Number: XA3S700A-4FGG400I
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400I

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 36: Switching Characteristics for the DLL
Notes:
1.
2.
3.
4.
5.
40
Output Frequency Ranges
CLKOUT_FREQ_CLK0
CLKOUT_FREQ_CLK90
CLKOUT_FREQ_2X
CLKOUT_FREQ_DV
Output Clock Jitter
CLKOUT_PER_JITT_0
CLKOUT_PER_JITT_90
CLKOUT_PER_JITT_180
CLKOUT_PER_JITT_270
CLKOUT_PER_JITT_2X
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Duty Cycle
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X,
Phase Alignment
CLKIN_CLKFB_PHASE
CLKOUT_PHASE_DLL
Lock Time
LOCK_DLL
Delay Lines
DCM_DELAY_STEP
The numbers in this table are based on the operating conditions set forth in
Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum
jitter of “±[1% of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns
is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250ps.
The typical delay step size is 23 ps.
Symbol
(4)
(3)
(4)
(2,3,4)
(5)
Frequency for the CLK0 and CLK180 outputs
Frequency for the CLK90 and CLK270 outputs
Frequency for the CLK2X and CLK2X180 outputs
Frequency for the CLKDV output
Period jitter at the CLK0 output
Period jitter at the CLK90 output
Period jitter at the CLK180 output
Period jitter at the CLK270 output
Period jitter at the CLK2X and CLK2X180 outputs
Period jitter at the CLKDV output when performing integer division
Period jitter at the CLKDV output when performing non-integer division
CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree
duty-cycle distortion
Phase offset between the CLKIN and CLKFB inputs
Phase offset between DLL outputs
When using the DLL alone: The time
from deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM is
locked, the CLKIN and CLKFB signals
are in phase
Finest delay resolution, averaged over all steps
Description
www.xilinx.com
5 MHz < F
F
Table 8
(not CLK2X180)
CLK0 to CLK2X
CLKIN
All others
CLKIN
> 15 MHz
and
< 15 MHz
Table
35.
Device
All
All
All
All
All
All
0.3125
Min
Speed Grade
DS681 (v1.1) February 3, 2009
10
15
–
–
–
–
–
–
–
–
–
–
–
–
–
5
5
-4
of CLKIN
of CLKIN
±[1% of
±[1% of
±[1% of
±[0.5%
±[0.5%
CLKIN
CLKIN
CLKIN
period
+ 100]
period
+ 100]
period
+ 350]
period
+ 100]
period
+ 150]
±100
±150
±150
±150
±150
±150
Product Specification
Max
250
200
334
166
600
35
5
Units
MHz
MHz
MHz
MHz
ms
μs
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
R