XC5VSX50T-2FF665C Xilinx Inc, XC5VSX50T-2FF665C Datasheet - Page 37

IC FPGA VIRTEX-5 50K 665FCBGA

XC5VSX50T-2FF665C

Manufacturer Part Number
XC5VSX50T-2FF665C
Description
IC FPGA VIRTEX-5 50K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-2FF665C

Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 58
shows the test setup parameters used for measuring input delay.
Table 58: Input Delay Measurement Methodology
Description
LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS, 1.2V
PCI (Peripheral Component Interconnect),
33 MHz, 3.3V
PCI, 66 MHz, 3.3V
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL, Class III & IV
HSTL, Class I & II, 1.8V
HSTL, Class III & IV, 1.8V
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL, Class I & II, 2.5V
SSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25
LVDSEXT (LVDS Extended Mode), 2.5V
LDT (HyperTransport), 2.5V
LVPECL (Low-Voltage Positive Emitter-Coupled
Logic), 2.5V
Notes:
1.
The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI
standards are the same for the corresponding non-DCI standards.
2.
Input waveform switches between V
and V
L
3.
Measurements are made at typical, minimum, and maximum V
listed are typical.
4.
Input voltage level from which measurement starts.
5.
This is an input voltage reference that bears no relation to the V
6.
The value given is the differential input voltage.
DS202 (v5.3) May 5, 2010
Product Specification
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(1,2)
I/O Standard Attribute
V
L
0
LVCMOS33
0
LVCMOS25
0
LVCMOS18
0
LVCMOS15
0
LVCMOS12
0
PCI33_3
PCI66_3
PCIX
GTL
V
– 0.2
REF
GTLP
V
– 0.2
REF
HSTL_I, HSTL_II
V
– 0.5
REF
HSTL_III, HSTL_IV
V
– 0.5
REF
HSTL_I_18, HSTL_II_18
V
– 0.5
REF
HSTL_III_18, HSTL_IV_18
V
– 0.5
REF
SSTL3_I, SSTL3_II
V
– 1.00
REF
SSTL2_I, SSTL2_II
V
– 0.75
REF
SSTL18_I, SSTL18_II
V
– 0.5
REF
AGP
V
– (0.2 xV
REF
1.2 – 0.125
LVDSEXT_25
1.2 – 0.125
LDT_25
0.6 – 0.125
LVPECL_25
1.15 – 0.3
.
H
values. Reported delays reflect worst case of these measurements. V
REF
/ V
parameters found in IBIS models and/or noted in
REF
MEAS
www.xilinx.com
(1,2)
(1,4,5)
V
V
H
MEAS
3.0
1.4
3.3
1.65
2.5
1.25
1.8
0.9
1.5
0.75
1.2
0.6
Per PCI™ Specification
Per PCI Specification
Per PCI-X™ Specification
V
+ 0.2
V
REF
REF
V
+ 0.2
V
REF
REF
V
+ 0.5
V
REF
REF
V
+ 0.5
V
REF
REF
V
+ 0.5
V
REF
REF
V
+ 0.5
V
REF
REF
V
+ 1.00
V
REF
REF
V
+ 0.75
V
REF
REF
V
+ 0.5
V
REF
REF
) V
+ (0.2 xV
)
V
AGP Spec
CCO
REF
CCO
REF
(6)
1.2 + 0.125
0
(6)
1.2 + 0.125
0
(6)
0.6 + 0.125
0
(6)
1.15 – 0.3
0
Figure
11.
(1,3,5)
V
REF
0.80
1.0
0.75
0.90
0.90
1.08
1.5
1.25
0.90
values
REF
37

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