MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 104

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

interrupt (as programmed by the SWRI bit in the SYPCR). The address of the interrupt
service routine for the software watchdog interrupt is stored in the software interrupt vector
register (SWIV). Figure 4-3 shows a block diagram of the software watchdog as well as
the clock control circuits for the periodic interrupt timer.
The watchdog clock rate is determined by the SWP bit in the periodic interrupt timer
register (PITR) and the SWT bits in the SYPCR. See Table 4-7 for a list of watchdog
timeout periods.
The software watchdog service sequence consists of the following steps: 1) write $55 to
the software service register (SWSR) and 2) write $AA to the SWSR. Both writes must
occur in the order listed prior to the watchdog timeout, but any number of instructions or
accesses to the SWSR can be executed between the two writes.
4.2.2.6 PERIODIC INTERRUPT TIMER. The periodic interrupt timer consists of an 8-bit
modulus counter that is loaded with the value contained in the PITR (see Figure
4-3). The modulus counter is clocked by a signal derived from the EXTAL input pin unless
an external frequency source is used. When an external frequency source is used
(MODCK low during reset), the default state of the prescaler control bits (SWP and PTP)
in the PITR is changed to enable both prescalers.
Either clock source (EXTAL or EXTAL
counter (PITCLK). When the modulus counter value reaches zero, an interrupt is
generated. The level of the generated interrupt is programmed into the PIRQL bits in the
periodic interrupt control register (PICR). During the IACK cycle, the SIM40 places the
periodic interrupt vector, programmed into the PIV bits in the PICR, onto the internal bus.
The value of bits 7–0 in the PITR is then loaded again into the modulus counter, and the
counting process starts over. If a new value is written to the PITR, this value is loaded into
the modulus counter when the current count is completed.
MOTOROLA
FREEZE
LPSTOP
EXTAL
SWP
PTP
DISABLE
CLOCK
Figure 4-3. Software Watchdog Block Diagram
PRESCALER (2 )
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PRECLK
CLOCK
512) is divided by 4 before driving the modulus
MUX
.
.
SWCLK
4
PITCLK
15 STAGE DIVIDER CHAIN (2 )
2
9
MODULUS COUNTER
2
11
PITR
2
13
RESET
2
15
15
PIT
INTERRUPT
4- 7