MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 127

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

4.3.4.1 BASE ADDRESS REGISTERS. There are four 32-bit base address registers in
the chip select function, one for each chip select signal.
Base Address 1
Base Address 2
U = Unaffected by reset
BA31–BA8—Base Address Bits 31–8
BFC3–BFC0—Base Function Code Bits 3–0
WP—Write Protect
FTE—Fast-Termination Enable
4-30
RESET:
RESET:
BA31
BA15
31
31
U
U
The base address field, the upper 24 bits of each base address register, selects the
starting address for the chip select. The specified base address must be on a multiple of
the selected block size. The corresponding bits, AM31–AM8, in the address mask
register define the size of the block for the chip select. The base address field (and the
base function code field) is compared to the address on the address bus to determine if
a chip select should be generated.
The value programmed into this field causes a chip select to be asserted for a certain
address space type. There are nine function code address spaces (see Section 3 Bus
Operation) specified as either user or supervisor, program or data, CPU, and DMA.
These bits should be used to allow access to one type of address space. If access to
more than one type of address space is desired, the FCMx bits should be used in
addition to the BFCx bits. To prevent access to CPU space, set the NCS bit.
This bit can restrict write accesses to the address range in a base address register. An
attempt to write to the range of addresses specified in a base address register that has
this bit set returns BERR .
This bit causes the cycle to terminate early with an internal DSACK , giving a fast two-
clock external access. When clear, all external cycles are at least three clocks. If fast
termination is enabled, the DD bits of the corresponding address mask register are
overridden (see Section 3 Bus Operation).
1 = Only read accesses are allowed.
0 = Either read or write accesses are allowed.
1 = Fast termination cycle enabled (termination determined by PS bits).
0 = Fast termination cycle disabled (termination determined by DD and PS bits).
BA30
BA14
30
30
U
U
BA29
BA13
29
29
U
U
BA28
BA12
28
28
U
U
BA27
BA11
27
27
Freescale Semiconductor, Inc.
U
U
For More Information On This Product,
BA26
BA10
26
26
U
U
MC68340 USER’S MANUAL
Go to: www.freescale.com
BA25
BA9
25
25
U
U
BA24
BA8
24
24
U
U
BFC3
BA23
23
23
U
U
BFC2
BA22
22
22
U
U
BFC1
BA21
21
21
U
U
BFC0
BA20
20
20
U
U
$044, $04C, $054, $05C
$046, $04E, $056, $05E
BA19
WP
19
19
U
U
Supervisor Only
Supervisor Only
BA18
FTE
18
18
U
U
MOTOROLA
BA17
NCS
17
17
U
0
BA16
16
16
U
V
0