MC68340AG16E Freescale Semiconductor, MC68340AG16E Datasheet - Page 280

• Manufacturer Part Number: MC68340AG16E
• Description: IC MPU 32BIT 16MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68340AG16E

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• No. Of I/o's: 16
• Cpu Speed: 16MHz
• No. Of Timers: 2
• Embedded Interface Type: UART
• Digital Ic Case Style: LQFP
• Rohs Compliant: Yes
• Processor Series: M683xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Details

S/D—Single-/Dual-Address Transfer
STR—Start
6.7.4 Channel Status Register (CSR)
The CSR contains the channel status information. This register is accessible in either
supervisor or user space. The CSR can always be read or written to when the DMA
module is enabled (i.e., the STP bit in the MCR is cleared).
6-30
This bit is cleared by a hardware/software reset, writing a logic zero, or setting one of
the following CSR bits: DONE, BES, BED, CONF, or BRKP. The STR bit cannot be set
when the CSR IRQ bit is set. The DMA channel cannot be started until the CSR DONE,
BES, BED, CONF, and BRKP bits are cleared.
Internal Request Mode:
External Request Mode:
1 = The DMA channel runs single-address transfers from a peripheral to memory or
0 = The DMA channel runs dual-address transfers.
1 = The DMA transfer starts as soon as this bit is set.
0 = The DMA transfer can be stopped by clearing this bit.
1 = Setting this bit allows the DMA to start the transfer when a DREQ input is
0 = The DMA transfer can be stopped by clearing this bit.
from memory to a peripheral. The destination holding register is not used for
these transfers because the data is transferred directly into the destination
location. The MC68340 on-chip peripherals do not support single-address
transfers.
received from an external device.
If any fields in the CCR are modified while the channel is
active, that change is effective immediately. To avoid any
problems with changing the setup for the DMA channel, a zero
should be written to the STR bit in the CCR to halt the DMA
channel at the end of the current bus cycle.
CSR1, CSR2
Supervisor/User
RESET
IRQ
Freescale Semiconductor, Inc.
7
0
For More Information On This Product,
DONE
6
0
MC68340 USER’S MANUAL
Go to: www.freescale.com
BES
5
0
BED
4
0
NOTE
CONF
3
0
BRKP
2
0
$78A, $7AA
1
0
0
0
0
0
MOTOROLA