CS80C286-12 Intersil, CS80C286-12 Datasheet - Page 26

• Manufacturer Part Number: CS80C286-12
• Description: IC CPU 16BIT 5V 12.5MHZ 68-PLCC
• Manufacturer: Intersil

Specifications of CS80C286-12

• Processor Type: 80C286 16-Bit
• Speed: 12.5MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 68-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

System Interface
The 80C286 system interface appears in two forms: a local
bus and a system bus. The local bus consists of address,
data, status, and control signals at the pins of the CPU. A sys-
tem bus is any buffered version of the local bus. A system bus
may also differ from the local bus in terms of coding of status
and control lines and/or timing and loading of signals.
PROGRAM INVISIBLE
TR
23
TASK REGISTER
15
15
BASE
LIMIT
CPU
0
0
0
SYSTEM
SEGMENT
DESCRIPTOR
FIGURE 18. TASK STATE SEGMENT AND TSS REGISTERS
TASK
STATE
SEGMENT
P D
15
TASK LDT SELECTOR
DS SELECTOR
SS SELECTOR
CS SELECTOR
ES SELECTOR
DI
SI
BP
SP
BX
DX
CX
AX
FLAG WORD
IP (ENTRY POINT)
SS FOR CPL 2
SP FOR CPL 2
SS FOR CPL 1
SP FOR CPL 1
SS FOR CPL 0
SP FOR CPL 0
BACK LINK SELECTOR TO TSS
P
L
0 TYPE
80C286
RESERVED
BASE
LIMIT
26
15 - 0
15 - 0
BASE
Bus Interface Signals and Timing
The 80C286 microsystems local bus interfaces the 80C286 to
local memory and I/O components. The interface has 24
address lines, 16 data lines, and 8 status and control signals.
The 80C286 CPU, 82C284 clock generator, 82C288 bus
controller, 82289 bus arbiter, 82C86H/87H transceivers, and
82C82/83H latches provide a buffered and decoded system
bus interface. The 82C284 generates the system clock and
23 - 16
0
BYTE
OFFSET
42
40
38
36
34
32
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
CURRENT
TASK
STATE
INITIAL
STACKS
FOR CPL 0, 1, 2
TYPE
1
3
P
1
0
An available task state segment.
May be used as the destination
of a task switch operation.
A busy task state segment. Can-
not be used as the destination of
a task switch.
Base and Limit fields are valid.
Segment is not present in mem-
ory, Base and Limit are not de-
fined.
DESCRIPTION
DESCRIPTION