A80960CF33 Intel, A80960CF33 Datasheet - Page 13

• Manufacturer Part Number: A80960CF33
• Description: IC MPU I960CF 33MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CF33

• Processor Type: i960
• Features: CF suffix, 32-Bit with DMA, 4K Cache
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Family Name: 80960
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803084

Datasheet
Table 3. 80960CF Pin Description—External Bus Signals (Sheet 2 of 2)
HOLDA
BLAST
LOCK
HOLD
BREQ
Name
BOFF
DT/R
DMA
DEN
SUP
D/C
Type
R(Q)
H(Q)
H(Z)
H(Z)
H(Z)
H(Z)
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
H(Z)
R(Z)
R(0)
R(0)
R(1)
R(1)
S(L)
S(L)
H(1)
R(0)
O
O
O
O
O
O
O
O
O
S
S
S
S
S
S
S
S
S
I
I
BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the last
data transfer of burst and non-burst accesses after the wait state counter reaches zero.
BLAST remains asserted until the clock following the last cycle of the last data transfer
of a bus access. When the READY or BTERM input is used to extend wait states, the
BLAST signal remains asserted until READY or BTERM terminates the access.
DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in
conjunction with DEN to provide control for data transceivers attached to the external
bus. When DT/R is asserted, the signal indicates that the processor receives data.
Conversely, when deasserted, the processor sends data. DT/R changes only while DEN
is high.
DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of
the bus request first data cycle and is deasserted at the end of the last data cycle. DEN
is used in conjunction with DT/R to provide control for data transceivers attached to the
external bus. DEN remains asserted for sequential reads from pipelined memory
regions. DEN is deasserted when DT/R changes.
BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK
may be used to prevent external agents from accessing memory which is currently
involved in an atomic operation. LOCK is asserted in the first clock of an atomic
operation and deasserted in the clock cycle following the last bus access for the atomic
operation. To allow the most flexibility for memory system enforcement of locked
accesses, the processor acknowledges a bus hold request when LOCK is asserted.
The processor performs DMA transfers while LOCK is active.
HOLD REQUEST signals that an external agent requests access to the external bus.
The processor asserts HOLDA after completing the current bus request. HOLD, HOLDA
and BREQ are used together to arbitrate access to the processor’s external bus by
external bus agents.
BUS BACKOFF, when asserted, suspends the current access and causes the bus pins
to float. When BOFF is deasserted, the ADS signal is asserted on the next clock cycle
and the access is resumed.
HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has
relinquished control of the external bus. When HOLDA is asserted, the external address
bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ are
used together to arbitrate access to the processor’s external bus by external bus
agents. Since the processor grants HOLD requests and enters the Hold Acknowledge
state even while RESET is asserted, the state of the HOLDA pin is independent of the
RESET pin.
BUS REQUEST is asserted when the bus controller has a request pending. BREQ may
be used by external bus arbitration logic in conjunction with HOLD and HOLDA to
determine when to return mastership of the external bus to the processor.
DATA OR CODE is asserted for a data request and deasserted for instruction requests.
D/C has the same timing as W/R.
DMA ACCESS indicates whether the bus request was initiated by the DMA controller.
DMA is asserted for any DMA request. DMA is deasserted for all other requests.
SUPERVISOR ACCESS indicates whether the bus request is issued while in supervisor
mode. SUP is asserted when the request has supervisor privileges and is deasserted
otherwise. SUP may be used to isolate supervisor code and data structures from non-
supervisor requests.
Description
80960-40, -33, -25
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