A80960CF33 Intel, A80960CF33 Datasheet - Page 66

• Manufacturer Part Number: A80960CF33
• Description: IC MPU I960CF 33MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CF33

• Processor Type: i960
• Features: CF suffix, 32-Bit with DMA, 4K Cache
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Family Name: 80960
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803084

80960-40, -33, -25
66
Figure 44. DREQ and DACK Functional Timing
Figure 45. EOP Functional Timing
(All Modes)
&
! (
&
Note: EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge
PCLK2:1
PCLK2:1
READY
(Case 1)
(Case 2)
BLAST
EOP
!WAIT
DREQx
DREQx
Note:
1. Case 1: DREQ must deassert before DACK deasserts. This applies to all Fly-By modes: source synchronized
2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.
3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus
DACKx
packing modes and destination synchronized unpacking modes.
This applies to all other DMA transfers.
accesses (defined by ADS and BLAST).
ADS
triggered. EOP
)
2 CLKs Min
must be
held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.
(see Note)
high to prevent next bus cycle
t
IS6
high to prevent next bus cycle
15 CLKs Max
t
IH6
t
IS6
t
IH6
System
Clock
Start DMA
Bus Request
End DMA
Bus Request
DMA
Acknowledge
DMA
Request
Datasheet
F_CX045A
F_CX018A