A80960CF33 Intel, A80960CF33 Datasheet - Page 8

• Manufacturer Part Number: A80960CF33
• Description: IC MPU I960CF 33MHZ 168-PGA
• Manufacturer: Intel

Specifications of A80960CF33

• Processor Type: i960
• Features: CF suffix, 32-Bit with DMA, 4K Cache
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 168-PGA
• Family Name: 80960
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 168
• Package Type: CPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 803084

80960-40, -33, -25
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The 80960CF, object code compatible with the 32-bit 80960 core Architecture, employs Special
Function Register extensions to control on-chip peripherals and instruction set extensions to shift
64-bit operands and configure on-chip hardware. Multiple 128-bit internal buses, on-chip
instruction caching and a sophisticated instruction scheduler allow the processor to sustain
execution of two instructions per clock with peak execution of three instructions per clock.
A 32-bit demultiplexed and pipelined burst bus provides a 132 Mbyte/s bandwidth to a system’s
high-speed external memory subsystem. Also, the 80960CF’s on-chip caching of instructions,
procedure context and critical program data substantially decouples system performance from the
wait states associated with accesses to the system’s slower, cost sensitive, main memory
subsystem.
The 80960CF bus controller integrates full wait state and bus width control for highest system
performance with minimal system design complexity. Unaligned access and Big Endian byte order
support reduces the cost of porting existing applications to the 80960CF.
The processor also integrates four complete data-chaining DMA channels and a high-speed
interrupt controller on-chip. DMA channels perform single-cycle or two-cycle transfers, data
packing and unpacking and data chaining. Block transfers — in addition to source or destination
synchronized transfers — are supported.
The interrupt controller provides full programmability of 248 interrupt sources into 32 priority
levels with a typical interrupt task switch (latency) time of 625 ns.
The 80960C-Series Core
The C-Series core is a very high performance microarchitectural implementation of the 80960 Core
Architecture. This core may sustain execution of two instructions per clock (80 MIPS at 40 MHz).
To achieve this level of performance, Intel has incorporated state-of-the-art silicon technology and
innovative microarchitectural constructs into the C-Series core implementation. Factors that
contribute to the core’s performance include:
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Parallel instruction decoding allows issuance of up to three instructions per clock.
Single-clock execution of most instructions
Parallel instruction decode allows sustained, simultaneous execution of two single-clock
instructions every clock cycle.
Efficient instruction pipeline minimizes pipeline break losses.
Register and resource scoreboarding allow simultaneous multi-clock instruction execution.
Branch look-ahead and prediction allows many branches to execute with no pipeline break.
Local Register Cache integrated on-chip caches Call/Return context.
Two-way set associative, 4 Kbyte integrated instruction cache
1 Kbyte integrated Data RAM sustains a four-word (128-bit) access every clock cycle.
Direct mapped, 1 Kbyte data cache, write through, write allocate
Datasheet